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    Integrated Circuit Die Having Input and Output Circuit Pads, Test Circuitry, and Multiplex Circuitry
    1.
    发明申请
    Integrated Circuit Die Having Input and Output Circuit Pads, Test Circuitry, and Multiplex Circuitry 有权
    具有输入和输出电路板，测试电路和多路复用电路的集成电路芯片

    公开(公告)号：US20140055158A1

    公开(公告)日：2014-02-27

    申请号：US14068819

    申请日：2013-10-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel ,  Alan Hales

    IPC: G01R1/073

    CPC classification number: G01R31/3177 ,  G01R1/07342 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31924 ,  G01R31/31926

    Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

    Abstract translation: 位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。 来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。 还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。 信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出 芯片/ IC输出。 除功能测试外，还可以对芯片和IC进行扫描测试。

    SCAN TESTING SYSTEM, METHOD AND APPARATUS
    4.
    发明申请
    SCAN TESTING SYSTEM, METHOD AND APPARATUS 审中-公开

    公开(公告)号：US20150309117A1

    公开(公告)日：2015-10-29

    申请号：US14792384

    申请日：2015-07-06

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel ,  Alan Hales

    IPC: G01R31/3185

    CPC classification number: G01R31/3177 ,  G01R1/07342 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31924 ,  G01R31/31926

    Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

    SCAN TESTING SYSTEM, METHOD AND APPARATUS
    5.
    发明申请
    SCAN TESTING SYSTEM, METHOD AND APPARATUS 审中-公开

    公开(公告)号：US20150012790A1

    公开(公告)日：2015-01-08

    申请号：US14494092

    申请日：2014-09-23

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel ,  Alan Hales

    IPC: G01R31/3185

    CPC classification number: G01R31/3177 ,  G01R1/07342 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31924 ,  G01R31/31926

    Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

    Integrated circuit wafer having plural dies with each die including test circuit receiving expected data and mask data from different pads
    6.
    发明授权
    Integrated circuit wafer having plural dies with each die including test circuit receiving expected data and mask data from different pads 有权
    具有多个管芯的集成电路晶片，每个管芯包括测试电路接收来自不同焊盘的预期数据和掩模数据

    公开(公告)号：US09562946B2

    公开(公告)日：2017-02-07

    申请号：US15078039

    申请日：2016-03-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel ,  Alan Hales

    IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/319 ,  G01R1/073

    CPC classification number: G01R31/3177 ,  G01R1/07342 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31924 ,  G01R31/31926

    Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

    Abstract translation: 位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。 来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。 还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。 信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出 芯片/ IC输出。 除功能测试外，还可以对芯片和IC进行扫描测试。

    Integrated circuit with plural comparators receiving expected data and mask data from different pads
    7.
    发明授权
    Integrated circuit with plural comparators receiving expected data and mask data from different pads 有权
    具有多个比较器的集成电路接收来自不同焊盘的预期数据和掩模数据

    公开(公告)号：US09103885B2

    公开(公告)日：2015-08-11

    申请号：US14494092

    申请日：2014-09-23

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel ,  Alan Hales

    IPC: H01L23/58 ,  G01R31/26 ,  G01R31/3185 ,  G01R31/319 ,  G01R1/073

    CPC classification number: G01R31/3177 ,  G01R1/07342 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31924 ,  G01R31/31926

    Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

    Abstract translation: 位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。 来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。 还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。 信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3）都可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出 芯片/ IC输出。 除功能测试外，还可以对芯片和IC进行扫描测试。

    Integrated circuit die having input and output circuit pads, test circuitry, and multiplex circuitry
    8.
    发明授权
    Integrated circuit die having input and output circuit pads, test circuitry, and multiplex circuitry 有权
    具有输入和输出电路板，测试电路和多路复用电路的集成电路管芯

    公开(公告)号：US08692248B2

    公开(公告)日：2014-04-08

    申请号：US14068819

    申请日：2013-10-31

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel ,  Alan Hales

    IPC: H01L23/58 ,  G01R31/26

    CPC classification number: G01R31/3177 ,  G01R1/07342 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31924 ,  G01R31/31926

    Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

    Abstract translation: 位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。 来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。 还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。 信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出 芯片/ IC输出。 除功能测试外，还可以对芯片和IC进行扫描测试。

    SCAN TESTING SYSTEM, METHOD AND APPARATUS
    10.
    发明申请
    SCAN TESTING SYSTEM, METHOD AND APPARATUS 审中-公开

    公开(公告)号：US20160202319A1

    公开(公告)日：2016-07-14

    申请号：US15078039

    申请日：2016-03-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel ,  Alan Hales

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R1/07342 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31924 ,  G01R31/31926

    Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

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