公开(公告)号：US10128145B2

公开(公告)日：2018-11-13

申请号：US14220693

申请日：2014-03-20

Applicant: Texas Instruments Incorporated

Inventor： Kamel Benaissa ,  Amitava Chatterjee

IPC: H01L21/761 ,  H01L21/8234 ,  H01L29/8605 ,  H01L29/66 ,  H01L27/08 ,  H01L21/266 ,  H01L27/06

Abstract: Integrated circuits and manufacturing methods are presented for creating diffusion resistors (101, 103) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.

公开(公告)号：US09412668B2

公开(公告)日：2016-08-09

申请号：US14712148

申请日：2015-05-14

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

公开(公告)号：US09245755B2

公开(公告)日：2016-01-26

申请号：US14575552

申请日：2014-12-18

Applicant: Texas Instruments Incorporated

Inventor： Brian E. Hornung ,  Xiang-Zheng Bo ,  Amitava Chatterjee ,  Alwin J. Tsao

IPC: H01L27/07 ,  H01L21/265 ,  H01L29/732 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/1004 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66272 ,  H01L29/6659 ,  H01L29/732 ,  H01L29/7833

Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.

公开(公告)号：US20180350795A1

公开(公告)日：2018-12-06

申请号：US16054037

申请日：2018-08-03

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/10

CPC classification number: H01L27/0262 ,  H01L29/1012 ,  H01L29/7424 ,  H01L29/7436

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

公开(公告)号：US20180350794A1

公开(公告)日：2018-12-06

申请号：US16053985

申请日：2018-08-03

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/10

CPC classification number: H01L27/0262 ,  H01L29/1012 ,  H01L29/7424 ,  H01L29/7436

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

公开(公告)号：US10083951B2

公开(公告)日：2018-09-25

申请号：US14750339

申请日：2015-06-25

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/74

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

公开(公告)号：US09461035B2

公开(公告)日：2016-10-04

申请号：US14134312

申请日：2013-12-19

Applicant: Texas Instruments Incorporated

Inventor： Derek W. Robinson ,  Amitava Chatterjee

IPC: H01L27/06 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/732 ,  H01L29/10 ,  H01L21/761 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L21/8249 ,  H01L21/761 ,  H01L21/76229 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/66659 ,  H01L29/732 ,  H01L29/7322 ,  H01L29/7833 ,  H01L29/7835

Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.

Abstract translation: 包含隔离的n沟道DEMOS晶体管和隔离的垂直PNP晶体管的CMOS集成电路具有深n型阱和周围的浅N型阱，提供与p型衬底的隔离。 隔离的n沟道DEMOS晶体管具有提供扩展漏极的上n型层，以及将下延伸的漏极与下面的深n型阱隔离的较低p型层。 隔离的垂直PNP晶体管具有提供基极的上n型层和提供集电极的下p型层。 具有相反极性的晶体管的CMOS集成电路可以通过掺杂剂类型中的适当反转来形成。

公开(公告)号：US20150249088A1

公开(公告)日：2015-09-03

申请号：US14712133

申请日：2015-05-14

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

公开(公告)号：US20150249040A1

公开(公告)日：2015-09-03

申请号：US14712148

申请日：2015-05-14

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/8238 ,  H01L21/265

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

Abstract translation: 第一类型的杂质原子通过栅极和薄栅极电介质注入到在沟道区的中间点处基本上仅具有第一类型的杂质原子的沟道区，以增加第一类杂质的平均掺杂浓度 通道区域中的原子来调节晶体管的阈值电压。

公开(公告)号：US20140124828A1

公开(公告)日：2014-05-08

申请号：US13668022

申请日：2012-11-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC: H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/1012 ,  H01L29/7424 ,  H01L29/7436

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

Abstract translation: 公开了一种用于集成电路的半导体可控整流器（图4A）。 半导体可控整流器包括具有第一导电类型（N）的第一轻掺杂区域（100）和在第一轻掺杂区域内形成的具有第二导电类型（P）的第一重掺杂区域（108）。 具有第二导电类型的第二轻掺杂区域（104）形成在第一轻掺杂区域附近。 在第二轻掺杂区域内形成具有第一导电类型的第二重掺杂区域（114）。 具有第一导电类型的掩埋层（101）形成在第二轻掺杂区域的下方并且电连接到第一轻掺杂区域。 在第二轻掺杂区域和第三重掺杂区域之间形成具有第二导电类型的第三轻掺杂区域（102）。 具有第二导电类型的第四轻掺杂区域（400）形成在第二轻掺杂区域和第三重掺杂区域之间，并且电连接到第二和第三轻掺杂区域。