公开(公告)号：US20240290828A1

公开(公告)日：2024-08-29

申请号：US18426051

申请日：2024-01-29

申请人： Littelfuse Semiconductor (Wuxi) Co., Ltd.

发明人： Xingchong Gu ,  Jifeng Zhou

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/0619 ,  H01L29/0834 ,  H01L29/1012 ,  H01L29/66363

摘要： Techniques for reducing peak on-state voltage of a semiconductor device fabricated in a wafer. A substrate layer is provided. An isolation structure is provided to laterally isolate the semiconductor device from other semiconductor devices in the wafer. A tub structure is formed in the substrate layer. A base layer is provided such that the base layer is disposed under the substrate layer. The base layer includes an anode having an associated active region that includes a drift region in the substrate layer. The tub structure is disposed inside the active region such that presence of the tub structure reduces a thickness of the drift region.

公开(公告)号：US20180350795A1

公开(公告)日：2018-12-06

申请号：US16054037

申请日：2018-08-03

申请人： Texas Instruments Incorporated

发明人： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L29/10

CPC分类号： H01L27/0262 ,  H01L29/1012 ,  H01L29/7424 ,  H01L29/7436

摘要： A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

公开(公告)号：US20180350794A1

公开(公告)日：2018-12-06

申请号：US16053985

申请日：2018-08-03

申请人： Texas Instruments Incorporated

发明人： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L29/10

CPC分类号： H01L27/0262 ,  H01L29/1012 ,  H01L29/7424 ,  H01L29/7436

摘要： A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

公开(公告)号：US09564441B2

公开(公告)日：2017-02-07

申请号：US14607025

申请日：2015-01-27

申请人： Kilopass Technology, Inc.

发明人： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC分类号： H01L27/102 ,  H01L29/06 ,  H01L29/10 ,  H01L27/11 ,  H01L21/768 ,  H01L21/8229 ,  H01L23/528 ,  H01L29/08 ,  G11C11/41 ,  G11C11/39 ,  G11C11/411 ,  H01L21/8249 ,  H01L27/06 ,  G11C11/412 ,  G11C11/419 ,  H01L27/082

CPC分类号： H01L27/1025 ,  G11C11/39 ,  G11C11/41 ,  G11C11/411 ,  G11C11/412 ,  G11C11/419 ,  H01L21/76229 ,  H01L21/768 ,  H01L21/8229 ,  H01L21/8249 ,  H01L23/528 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/083 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/735 ,  H01L29/737 ,  H01L29/7436 ,  H01L2924/0002 ,  H01L2924/00

摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

摘要翻译： 描述了基于用于SRAM集成电路的晶闸管的双晶体管存储单元及其制造方法。 存储器单元可以在具有浅沟槽隔离的半导体衬底中的晶闸管的MOS和双极选择晶体管的不同组合中实现，或者不具有选择晶体管。 标准CMOS工艺技术可用于制造SRAM。

公开(公告)号：US09455340B2

公开(公告)日：2016-09-27

申请号：US14843631

申请日：2015-09-02

申请人： ABB Schweiz AG

发明人： Munaf Rahimo

IPC分类号： H01L29/739 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08 ,  H01L29/745 ,  H01L29/749 ,  H01L27/06 ,  H01L29/06

CPC分类号： H01L29/7395 ,  H01L27/0623 ,  H01L29/0696 ,  H01L29/0813 ,  H01L29/0821 ,  H01L29/083 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/1016 ,  H01L29/102 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/7455 ,  H01L29/749

摘要： Power semiconductor device having a wafer, including emitter and collector electrodes arranged on opposite sides, wherein a gate electrode arranged on the emitter side has a conductive gate layer and an insulating layer arranged in the following order between the collector and emitter side: a p doped collector layer, an (n−) doped drift layer, an n doped enhancement layer, a p based base layer having a first and second base region, and an (n+) doped first and second emitter layer, wherein the emitter electrode contacts the first emitter layer and the first base region at an emitter contact area, wherein the second emitter layer is insulated from a direct contact to the emitter electrode by the insulating layer and wherein the second emitter layer is separated from the first emitter layer by the base layer.

摘要翻译： 具有晶片的功率半导体器件，包括布置在相对侧上的发射极和集电极，其中布置在发射极侧的栅电极具有在集电极和发射极侧之间按以下顺序布置的导电栅极层和绝缘层： （n）掺杂漂移层，n掺杂增强层，具有第一和第二基极区域的基于基底的基极层和掺杂（n +）的第一和第二发射极层，其中发射极电极接触第一发射极层 以及在发射极接触区域处的第一基极区域，其中第二发射极层通过绝缘层与发射极电极的直接接触绝缘，并且其中第二发射极层通过基极层与第一发射极层分离。

公开(公告)号：US20140124828A1

公开(公告)日：2014-05-08

申请号：US13668022

申请日：2012-11-02

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC分类号： H01L29/74

CPC分类号： H01L27/0262 ,  H01L29/1012 ,  H01L29/7424 ,  H01L29/7436

摘要： A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

摘要翻译： 公开了一种用于集成电路的半导体可控整流器（图4A）。 半导体可控整流器包括具有第一导电类型（N）的第一轻掺杂区域（100）和在第一轻掺杂区域内形成的具有第二导电类型（P）的第一重掺杂区域（108）。 具有第二导电类型的第二轻掺杂区域（104）形成在第一轻掺杂区域附近。 在第二轻掺杂区域内形成具有第一导电类型的第二重掺杂区域（114）。 具有第一导电类型的掩埋层（101）形成在第二轻掺杂区域的下方并且电连接到第一轻掺杂区域。 在第二轻掺杂区域和第三重掺杂区域之间形成具有第二导电类型的第三轻掺杂区域（102）。 具有第二导电类型的第四轻掺杂区域（400）形成在第二轻掺杂区域和第三重掺杂区域之间，并且电连接到第二和第三轻掺杂区域。

公开(公告)号：US06734496B2

公开(公告)日：2004-05-11

申请号：US10115995

申请日：2002-04-05

申请人： Tatsuhiko Fujihira

发明人： Tatsuhiko Fujihira

IPC分类号： H01L2976

CPC分类号： H01L29/7816 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0843 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/78696 ,  H01L29/808 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

公开(公告)号：US20020185708A1

公开(公告)日：2002-12-12

申请号：US09878605

申请日：2001-06-11

申请人： INTERNATIONAL BUSINESS MACHINES CORORATION

发明人： Douglas D. Coolbaugh ,  Kathryn T. Schonenberg

IPC分类号： H01L021/8222 ,  H01L027/082 ,  H01L027/102 ,  H01L029/70 ,  H01L031/11 ,  H01L021/331

CPC分类号： H01L29/7378 ,  H01L21/26506 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/66242 ,  H01L29/66318

摘要： A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

摘要翻译： 提供了一种改善SiGe双极性产率以及制造SiGe异质结双极晶体管的方法。 本发明的方法包括将碳C离子注入到器件的以下区域之一：集电极区域，子集电极区域，非本征基极区域和集电极 - 基极结区域。 在优选实施例中，上述每个区域包括C植入物。

公开(公告)号：US20020105026A1

公开(公告)日：2002-08-08

申请号：US10115997

申请日：2002-04-05

发明人： Tatsuhiko Fujihira

IPC分类号： H01L029/76 ,  H01L029/94

CPC分类号： H01L29/7816 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0843 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/78696 ,  H01L29/808 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.

公开(公告)号：US20240014302A1

公开(公告)日：2024-01-11

申请号：US18038643

申请日：2021-11-24

申请人： Hitachi Energy Switzerland AG

发明人： Jan VOBECKY

IPC分类号： H01L29/747 ,  H01L23/552 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L29/747 ,  H01L23/552 ,  H01L29/0692 ,  H01L29/1012 ,  H01L29/42308

摘要： Bidirectional thyristor device comprising a semiconductor body extending in a vertical direction between a first main surface and a second main surface opposite the first main surface, a first main electrode arranged on the first main surface, and a second main electrode arranged on the second main surface, is specified, wherein the semiconductor body comprises a first base layer of a first conductivity type, a second base layer of the first conductivity type, and a third base layer of a second conductivity type different than the first conductivity type arranged between the first base layer and the second base layer. The first main electrode acts as a cathode for a first thyristor functional element and as an anode for a second thyristor functional element of the bidirectional thyristor device. The bidirectional thyristor device is configured asymmetrically with respect to the first thyristor functional element and the second thyristor functional element.