公开(公告)号：US12057443B2

公开(公告)日：2024-08-06

申请号：US17687380

申请日：2022-03-04

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Amitava Chatterjee ,  Xiaoju Wu

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/1012 ,  H01L29/7424 ,  H01L29/7436

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region. A fourth lightly doped region (400) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region and electrically connected to the second and third lightly doped regions.

公开(公告)号：US10461072B2

公开(公告)日：2019-10-29

申请号：US15895694

申请日：2018-02-13

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Akram A. Salman ,  Binghua Hu

IPC: H01L21/762 ,  H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L21/763 ,  H01L21/8222 ,  H01L27/06

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

公开(公告)号：US10396199B2

公开(公告)日：2019-08-27

申请号：US15624741

申请日：2017-06-16

Applicant: Texas Instruments Incorporated

Inventor： Aravind C. Appaswamy ,  Akram A. Salman ,  Farzan Farbiz ,  Gianluca Boselli

IPC: H02H9/00 ,  H01L29/78 ,  H01L27/02 ,  H01L29/10

Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.

公开(公告)号：US10269898B2

公开(公告)日：2019-04-23

申请号：US14713867

申请日：2015-05-15

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Akram A. Salman

IPC: H01L29/866 ,  H01L29/06 ,  H01L29/73 ,  H01L29/417 ,  H01L27/02

Abstract: A surrounded emitter bipolar device includes a substrate having a p-epitaxial (p-epi) layer thereon, and a p-base in the p-epi layer. A two dimensional (2D) array of p-base contacts (base units) include the p-base, wherein each base unit includes an outer dielectric structure surrounding an inner dielectric isolation ring. The inner dielectric isolation ring surrounds an n region (n+moat). A first portion of the n+moats are collector (C) units, and a second portion of the n+moats are emitter (E) units. Each of the E units is separated from a nearest neighbor E unit by a C unit.

公开(公告)号：US20190109128A1

公开(公告)日：2019-04-11

申请号：US16210753

申请日：2018-12-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry L. Edwards ,  Akram A. Salman ,  Md Iqbal Mahmud

IPC: H01L27/02 ,  H01L29/06

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.

公开(公告)号：US10249610B1

公开(公告)日：2019-04-02

申请号：US15897020

申请日：2018-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind Chennimalai Appaswamy ,  James P. Di Sarro ,  Krishna Praveen Mysore Rajagopal ,  Akram A. Salman ,  Muhammad Yusuf Ali

IPC: H01L27/00 ,  H01L29/00 ,  H04L21/00 ,  H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/739

Abstract: In some examples, an electrostatic discharge (ESD) device comprises an insulated-gate bipolar transistor (IGBT) comprising a source terminal, an anode terminal, a gate terminal, and a body terminal; and at least one reverse bias device comprising a first terminal and a second terminal, wherein the first terminal couples to the source terminal and the second terminal couples to the body terminal.

公开(公告)号：US09818868B2

公开(公告)日：2017-11-14

申请号：US14543123

申请日：2014-11-17

Applicant: Texas Instruments Incorporated

Inventor： Aravind C. Appaswamy ,  Akram A. Salman ,  Farzan Farbiz

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/45 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L29/7835 ,  H01L27/027 ,  H01L29/0696 ,  H01L29/456 ,  H01L29/66659

Abstract: A drain extended metal oxide semiconductor (MOS) includes a substrate having a semiconductor. A gate is located on the semiconductor, a source is located on the semiconductor and on one side of the gate, and a drain is located on the semiconductor and on another side of said gate. The MOS includes least one first finger having a first finger drain component located adjacent the drain, the first finger drain component has a silicide layer. At least one second finger has a second finger drain component located adjacent the drain, the second finger drain component has less silicide than the first finger drain component.

公开(公告)号：US09754930B2

公开(公告)日：2017-09-05

申请号：US15292409

申请日：2016-10-13

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Akram A. Salman

IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/74 ,  H01L23/528

CPC classification number: H01L27/0262 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823892 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66371 ,  H01L29/742

Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

公开(公告)号：US09633991B2

公开(公告)日：2017-04-25

申请号：US14949417

申请日：2015-11-23

Applicant: Texas Instruments Incorporated

Inventor： Akram A. Salman ,  Farzan Farbiz ,  Ann Margaret Concannon ,  Gianluca Boselli

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0262 ,  H01L27/0248 ,  H01L27/0259 ,  H01L27/0266 ,  H02H9/046

Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.

公开(公告)号：US20150371985A1

公开(公告)日：2015-12-24

申请号：US14311205

申请日：2014-06-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Akram A. Salman ,  Md Iqbal Mahmud

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/747

CPC classification number: H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/456 ,  H01L29/66386 ,  H01L29/7436 ,  H01L29/747

Abstract: A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.

Abstract translation: 第一可控硅整流器具有在第一方向上的击穿电压和在第二方向上的击穿电压。 第二可控硅整流器具有在第一方向上具有比第一可控硅整流器更高的幅度的击穿电压，以及在第二方向上具有比第一可控硅整流器更低的幅度的击穿电压。 双向静电放电（ESD）结构利用了第一个可控硅整流器和第二个可控硅整流器来提供双向保护。