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    RECONFIGURABLE MATRIX MULTIPLIER SYSTEM AND METHOD
    2.
    发明申请
    RECONFIGURABLE MATRIX MULTIPLIER SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20180246855A1

    公开(公告)日：2018-08-30

    申请号：US15905250

    申请日：2018-02-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Arthur John Redfern ,  Donald Edward Steiss ,  Timothy David Anderson ,  Kai Chirca

    IPC: G06F17/16

    Abstract: A reconfigurable matrix multiplier (RMM) system/method allowing tight or loose coupling to supervisory control processor application control logic (ACL) in a system-on-a-chip (SOC) environment is disclosed. The RMM provides for C=A*B matrix multiplication operations having A-multiplier-matrix (AMM), B-multiplicand-matrix (BMM), and C-product-matrix (CPM), as well as C=A*B+D operations in which D-summation-matrix (DSM) represents the result of a previous multiplication operation or another previously defined matrix. The RMM provides for additional CPM LOAD/STORE paths allowing overlapping of compute/data transfer operations and provides for CPM data feedback to the AMM or BMM operand inputs from a previously calculated CPM result. The RMM anticipates the use of 8, 16, and 32-bit operand reconfigurable matrix datum in conjunction with a typical external memory bus data width of 512 bits and an instruction control unit (ICU) implemented using a series of RMM configuration words (RCW) and streaming opcode functions (SOF).

    MATRIX COMPRESSION ACCELERATOR SYSTEM AND METHOD
    4.
    发明公开
    MATRIX COMPRESSION ACCELERATOR SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20240333304A1

    公开(公告)日：2024-10-03

    申请号：US18738203

    申请日：2024-06-10

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Arthur John Redfern ,  Dan Wang

    IPC: H03M7/30 ,  G06F13/28 ,  G06F17/16 ,  G06N3/045 ,  G06N3/063

    CPC classification number: H03M7/30 ,  G06F13/28 ,  G06F17/16 ,  G06N3/063 ,  H03M7/3082 ,  H03M7/6029 ,  H03M7/6064 ,  G06N3/045

    Abstract: A matrix compression/decompression accelerator (MCA) system/method that coordinates lossless data compression (LDC) and lossless data decompression (LDD) transfers between an external data memory (EDM) and a local data memory (LDM) is disclosed. The system implements LDC using a 2D-to-1D transformation of 2D uncompressed data blocks (2DU) within LDM to generate 1D uncompressed data blocks (1DU). The 1DU is then compressed to generate a 1D compressed superblock (CSB) in LDM. This LDM CSB may then be written to EDM with a reduced number of EDM bus cycles. The system implements LDD using decompression of CSB data retrieved from EDM to generate a 1D decompressed data block (1DD) in LDM. A 1D-to-2D transformation is then applied to the LDM 1DD to generate a 2D decompressed data block (2DD) in LDM. This 2DD may then be operated on by a matrix compute engine (MCE) using a variety of function operators.

    MATRIX COMPRESSION ACCELERATOR SYSTEM AND METHOD
    6.
    发明申请
    MATRIX COMPRESSION ACCELERATOR SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20200304141A1

    公开(公告)日：2020-09-24

    申请号：US16899632

    申请日：2020-06-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Arthur John Redfern ,  Dan Wang

    IPC: H03M7/30 ,  G06F13/28 ,  G06F17/16 ,  G06N3/063

    Abstract: A matrix compression/decompression accelerator (MCA) system/method that coordinates lossless data compression (LDC) and lossless data decompression (LDD) transfers between an external data memory (EDM) and a local data memory (LDM) is disclosed. The system implements LDC using a 2D-to-1D transformation of 2D uncompressed data blocks (2DU) within LDM to generate 1D uncompressed data blocks (1DU). The 1DU is then compressed to generate a 1D compressed superblock (CSB) in LDM. This LDM CSB may then be written to EDM with a reduced number of EDM bus cycles. The system implements LDD using decompression of CSB data retrieved from EDM to generate a 1D decompressed data block (1DD) in LDM. A 1D-to-2D transformation is then applied to the LDM 1DD to generate a 2D decompressed data block (2DD) in LDM. This 2DD may then be operated on by a matrix compute engine (MCE) using a variety of function operators.

    Mixer Sequence Design for N-Path Filters
    7.
    发明申请
    Mixer Sequence Design for N-Path Filters 审中-公开
    N路径滤波器的混频器序列设计

    公开(公告)号：US20160164555A1

    公开(公告)日：2016-06-09

    申请号：US15044171

    申请日：2016-02-16

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Guolong Su ,  Arthur John Redfern

    IPC: H04B1/10 ,  H04B17/336 ,  H04W72/04

    CPC classification number: H04W72/0446 ,  H04B17/336

    Abstract: A bandpass filter includes a plurality of parallel paths. Each path includes a first mixer, a low-pass filter, and a second mixer. The first mixer in each path receives the input signal and mixes the input signal with a periodic mixer sequence. The low-pass filter in each path is operable to filter an output of the associated first mixer. The second mixer in each path is coupled to receive an output of the associated low-pass filter and mixes said filter output with a periodic mixer sequence having a period that is divided into a plurality of time slots, wherein again the mixer value is constant during each time slot. A summer sums the outputs of the second mixers of each of the paths to generate an output of the bandpass filter.

    Abstract translation: 带通滤波器包括多个平行路径。 每个路径包括第一混频器，低通滤波器和第二混频器。 每个路径中的第一个混频器接收输入信号，并将输入信号与周期性混频器序列混合。 每个路径中的低通滤波器可操作以对相关联的第一混频器的输出进行滤波。 每个路径中的第二混频器被耦合以接收相关联的低通滤波器的输出，并且将所述滤波器输出与具有被分成多个时隙的周期的周期性混频器序列混合，其中混频器值在 每个时间段 夏季对每个路径的第二混频器的输出求和，以产生带通滤波器的输出。

    Matrix transfer accelerator system and method
    8.
    发明授权
    Matrix transfer accelerator system and method 有权

    公开(公告)号：US12073105B2

    公开(公告)日：2024-08-27

    申请号：US17877518

    申请日：2022-07-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Arthur John Redfern ,  Asheesh Bhardwaj

    IPC: G06F3/06 ,  G06F15/00 ,  G06F17/16 ,  G06N3/045

    CPC classification number: G06F3/0647 ,  G06F3/0613 ,  G06F3/0683 ,  G06F15/00 ,  G06F17/16 ,  G06N3/045

    Abstract: A matrix transfer accelerator (MTA) system/method that coordinates data transfers between an external data memory (EDM) and a local data memory (LDM) using matrix tiling and/or grouping is disclosed. The system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits EDM-to-LDM data transfers with or without zero pad peripheral matrix filling. The system may incorporate an automated zero-fill direct memory access (DMA) controller (ZDC) that transfers data from the EDM to the LDM based on a set of DMA controller registers including data width register (DWR), transfer count register (TCR), fill count register (FCR), EDM source address register (ESR), and LDM target address register (LTR). The ZDC transfers matrix data from the EDM[ESR] to the LDM[LTR] such that EDM matrix data of DWR row data width is automatically zero-filled around a periphery of a matrix written to the LDM matrix based on the FCR value.

    MATRIX TRANSFER ACCELERATOR SYSTEM AND METHOD
    9.
    发明申请
    MATRIX TRANSFER ACCELERATOR SYSTEM AND METHOD 有权

    公开(公告)号：US20220365700A1

    公开(公告)日：2022-11-17

    申请号：US17877518

    申请日：2022-07-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Arthur John Redfern ,  Asheesh Bhadwaj

    IPC: G06F3/06 ,  G06F17/16 ,  G06F15/00

    Abstract: A matrix transfer accelerator (MTA) system/method that coordinates data transfers between an external data memory (EDM) and a local data memory (LDM) using matrix tiling and/or grouping is disclosed. The system utilizes foreground/background buffering that overlaps compute and data transfer operations and permits EDM-to-LDM data transfers with or without zero pad peripheral matrix filling. The system may incorporate an automated zero-fill direct memory access (DMA) controller (ZDC) that transfers data from the EDM to the LDM based on a set of DMA controller registers including data width register (DWR), transfer count register (TCR), fill count register (FCR), EDM source address register (ESR), and LDM target address register (LTR). The ZDC transfers matrix data from the EDM[ESR] to the LDM[LTR] such that EDM matrix data of DWR row data width is automatically zero-filled around a periphery of a matrix written to the LDM matrix based on the FCR value.

    MATRIX COMPRESSION ACCELERATOR SYSTEM AND METHOD
    10.
    发明申请
    MATRIX COMPRESSION ACCELERATOR SYSTEM AND METHOD 有权

    公开(公告)号：US20210194498A1

    公开(公告)日：2021-06-24

    申请号：US17195703

    申请日：2021-03-09

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Arthur John Redfern ,  Dan Wang

    IPC: H03M7/30 ,  G06F13/28 ,  G06F17/16 ,  G06N3/063

    Abstract: A matrix compression/decompression accelerator (MCA) system/method that coordinates lossless data compression (LDC) and lossless data decompression (LDD) transfers between an external data memory (EDM) and a local data memory (LDM) is disclosed. The system implements LDC using a 2D-to-1D transformation of 2D uncompressed data blocks (2DU) within LDM to generate 1D uncompressed data blocks (1DU). The 1DU is then compressed to generate a 1D compressed superblock (CSB) in LDM. This LDM CSB may then be written to EDM with a reduced number of EDM bus cycles. The system implements LDD using decompression of CSB data retrieved from EDM to generate a 1D decompressed data block (1DD) in LDM. A 1D-to-2D transformation is then applied to the LDM 1DD to generate a 2D decompressed data block (2DD) in LDM. This 2DD may then be operated on by a matrix compute engine (MCE) using a variety of function operators.

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