公开(公告)号：US12081221B2

公开(公告)日：2024-09-03

申请号：US17679978

申请日：2022-02-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Roger Elies

IPC: H03K5/24 ,  H03K19/0185

CPC classification number: H03K5/2481 ,  H03K19/018521

Abstract: A circuit includes a transistor input pair, a differential input having a comparator input, and a level shifter. The transistor input pair is adapted to be coupled between a voltage supply and a comparator output. The transistor input pair includes a first transistor having a gate and a drain. The drain of the first transistor is coupled to the comparator output. The level shifter is coupled between the transistor input pair and the differential input. The level shifter includes a second transistor having a gate and a source. The gate of the second transistor is coupled to the comparator input. The source of the second transistor is coupled to the gate of the first transistor.

公开(公告)号：US11658658B2

公开(公告)日：2023-05-23

申请号：US17700230

申请日：2022-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijit Kumar Das ,  Brian Roger Elies

IPC: H03K17/687

CPC classification number: H03K17/6871

Abstract: In some examples, a switch comprises first and second drain-extended transistors of a first type, third and fourth drain-extended transistors of a second type, a switch input coupled between drains of the first and third drain-extended transistors, a switch output coupled between drains of the second and fourth drain-extended transistors, and a control input. The control input is coupled to gates of the first and second drain-extended transistors, a first switch coupled to sources of the first and second drain-extended transistors, a second switch coupled between a voltage supply and gates of the third and fourth drain-extended transistors, and a third switch coupled between the voltage supply and sources of the third and fourth drain-extended transistors. The control input comprises a fifth drain-extended transistor coupled between the sources of the third and fourth drain-extended transistors and the gates of the third and fourth drain-extended transistors.

公开(公告)号：US20180123607A1

公开(公告)日：2018-05-03

申请号：US15691827

申请日：2017-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijit Kumar Das ,  Brian Roger Elies

IPC: H03M1/00 ,  H03M1/12

CPC classification number: H03M1/001 ,  G06F7/588 ,  H03M1/00 ,  H03M1/12 ,  H03M1/48

Abstract: An electronic circuit system with an input for receiving an analog signal having a frequency and comprising noise, that noise including input referred noise, and the noise fluctuates in a range. The system also comprises a signal path with: (i) an analog to digital converter for providing a digital output value in response to a clock period; (ii) a feedback node; and (iii) circuitry for limiting a signal swing at the feedback node, during a period of the clock period, to be no greater than an RMS value of the noise. The analog to digital converter is further for providing the digital output value in response to the analog signal and the signal swing at the feedback node.

公开(公告)号：US09780798B1

公开(公告)日：2017-10-03

申请号：US15339931

申请日：2016-11-01

Applicant: Texas Instruments Incorporated

Inventor： Abhijit Kumar Das ,  Brian Roger Elies

IPC: H03M1/00 ,  H03M1/12

CPC classification number: H03M1/001 ,  G06F7/588 ,  H03M1/00 ,  H03M1/12 ,  H03M1/48

Abstract: An electronic circuit system with an input for receiving an analog signal having a frequency and comprising noise, that noise including input referred noise, and the noise fluctuates in a range. The system also comprises a signal path with: (i) an analog to digital converter for providing a digital output value in response to a clock period; (ii) a feedback node; and (iii) circuitry for limiting a signal swing at the feedback node, during a period of the clock period, to be no greater than an RMS value of the noise. The analog to digital converter is further for providing the digital output value in response to the analog signal and the signal swing at the feedback node.