公开(公告)号：US20220406885A1

公开(公告)日：2022-12-22

申请号：US17489199

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： Jing Hu ,  Zhi Peng Feng ,  Chao Zuo ,  Dongsheng Liu ,  Yunlong Liu ,  Manoj K. Jain ,  Shengpin Yang

IPC: H01L49/02

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

公开(公告)号：US11888021B2

公开(公告)日：2024-01-30

申请号：US17489199

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： Jing Hu ,  Zhi Peng Feng ,  Chao Zuo ,  Dongsheng Liu ,  Yunlong Liu ,  Manoj K Jain ,  Shengpin Yang

IPC: H01L21/762 ,  H01L49/02 ,  H01L21/324 ,  H01L21/225 ,  H01L21/74 ,  H01L29/94 ,  H01L21/3215

CPC classification number: H01L28/87 ,  H01L21/2253 ,  H01L21/324 ,  H01L21/32155 ,  H01L21/743 ,  H01L21/76237 ,  H01L28/40 ,  H01L29/945

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

公开(公告)号：US20240120368A1

公开(公告)日：2024-04-11

申请号：US18543769

申请日：2023-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jing Hu ,  ZHI PENG Feng ,  Chao Zuo ,  Dongsheng Liu ,  Yunlong Liu ,  Manoj K Jain ,  Shengpin Yang

IPC: H01G4/224 ,  H01L21/225 ,  H01L21/3215 ,  H01L21/324 ,  H01L21/74 ,  H01L21/762 ,  H01L29/94

CPC classification number: H01L28/87 ,  H01L21/2253 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/743 ,  H01L21/76237 ,  H01L28/40 ,  H01L29/945

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.