公开(公告)号：US12080755B2

公开(公告)日：2024-09-03

申请号：US17512484

申请日：2021-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Yunlong Liu ,  Zhi Peng Feng ,  Rui Liu ,  Rui Song ,  Manoj K Jain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/495 ,  H01L27/08 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L28/92

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

公开(公告)号：US20240395854A1

公开(公告)日：2024-11-28

申请号：US18795747

申请日：2024-08-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Yunlong Liu ,  Zhi Peng Feng ,  Rui Liu ,  Rui Song ,  Manoj K Jain

IPC: H01G4/30

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

公开(公告)号：US20240120368A1

公开(公告)日：2024-04-11

申请号：US18543769

申请日：2023-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jing Hu ,  ZHI PENG Feng ,  Chao Zuo ,  Dongsheng Liu ,  Yunlong Liu ,  Manoj K Jain ,  Shengpin Yang

IPC: H01G4/224 ,  H01L21/225 ,  H01L21/3215 ,  H01L21/324 ,  H01L21/74 ,  H01L21/762 ,  H01L29/94

CPC classification number: H01L28/87 ,  H01L21/2253 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/743 ,  H01L21/76237 ,  H01L28/40 ,  H01L29/945

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

公开(公告)号：US20240258112A1

公开(公告)日：2024-08-01

申请号：US18103134

申请日：2023-01-30

Applicant: Texas Instruments Incorporated

Inventor： Chao Zuo ,  Jing Hu ,  Tian Ping Lv ,  Abbas Ali ,  Manoj K Jain

IPC: H01L21/3065

CPC classification number: H01L21/30655 ,  H01L28/40

Abstract: A method of forming an integrated circuit includes forming a plurality of openings in a resist layer over a semiconductor substrate and removing portions of a semiconductor surface layer exposed by the openings, thereby forming a plurality of deep trenches. Removing the portions includes performing a first etch loop for a first plurality of repetitions, the first etch loop including a deposition process executed for a first deposition time and an etch process executed for a first etch time. The removing further includes performing a second etch loop for a second plurality of repetitions, the second etch loop including the deposition process executed for a second deposition time and an etch process executed for a second etch time. The second deposition time is at least 10% greater than the first deposition time, and the second etch time is at least 10% greater than the first etch time.

公开(公告)号：US11888021B2

公开(公告)日：2024-01-30

申请号：US17489199

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： Jing Hu ,  Zhi Peng Feng ,  Chao Zuo ,  Dongsheng Liu ,  Yunlong Liu ,  Manoj K Jain ,  Shengpin Yang

IPC: H01L21/762 ,  H01L49/02 ,  H01L21/324 ,  H01L21/225 ,  H01L21/74 ,  H01L29/94 ,  H01L21/3215

CPC classification number: H01L28/87 ,  H01L21/2253 ,  H01L21/324 ,  H01L21/32155 ,  H01L21/743 ,  H01L21/76237 ,  H01L28/40 ,  H01L29/945

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.