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    Adhesion of ferroelectric material to underlying conductive capacitor plate
    4.
    发明授权
    Adhesion of ferroelectric material to underlying conductive capacitor plate 有权
    铁电材料粘附到底层导电电容器板上

    公开(公告)号：US09305998B2

    公开(公告)日：2016-04-05

    申请号：US14175838

    申请日：2014-02-07

    Applicant: Texas Instruments Incorporated

    Inventor： Bhaskar Srinivasan ,  Eric H. Warninghoff ,  Alan Merriam ,  Haowen Bu ,  Brian E. Goodlin ,  Manoj K. Jain

    IPC: H01L21/00 ,  H01L49/02 ,  H01L21/02 ,  C23C16/02 ,  C23C16/40 ,  H01L27/115

    CPC classification number: H01L28/75 ,  C23C16/0281 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/02304 ,  H01L27/11502 ,  H01L28/55

    Abstract: Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.

    Abstract translation: 在铱金属上沉积钛酸锆（PZT）铁电材料，在集成电路中形成铁电电容器。 通过沉积具有铱金属的下导电板层作为顶层形成电容器。 铱金属的表面在PZT材料沉积之前或期间被热氧化。 在铱金属表面的所得铱氧化物非常薄，几毫米数量级，这允许沉积的PZT根据铱金属的晶体结构而不是氧化铱的晶体结构成核。 氧化铱也具有中等化学计量（IrO2-x），并与沉积的PZT材料发生反应。

    Adhesion of Ferroelectric Material to Underlying Conductive Capacitor Plate
    5.
    发明申请
    Adhesion of Ferroelectric Material to Underlying Conductive Capacitor Plate 有权
    铁电材料对底层导电电容器板的附着力

    公开(公告)号：US20140227805A1

    公开(公告)日：2014-08-14

    申请号：US14175838

    申请日：2014-02-07

    Applicant: Texas Instruments Incorporated

    Inventor： Bhaskar Srinivasan ,  Eric H. Warninghoff ,  Alan Merriam ,  Haowen Bu ,  Brian E. Goodlin ,  Manoj K. Jain

    IPC: H01L49/02

    CPC classification number: H01L28/75 ,  C23C16/0281 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/02271 ,  H01L21/02304 ,  H01L27/11502 ,  H01L28/55

    Abstract: Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.

    Abstract translation: 在铱金属上沉积钛酸锆（PZT）铁电材料，在集成电路中形成铁电电容器。 通过沉积具有铱金属的下导电板层作为顶层形成电容器。 铱金属的表面在PZT材料沉积之前或期间被热氧化。 在铱金属表面的所得铱氧化物非常薄，几毫米数量级，这允许沉积的PZT根据铱金属的晶体结构而不是氧化铱的晶体结构成核。 氧化铱也具有中等化学计量（IrO2-x），并与沉积的PZT材料发生反应。

    METHOD OF USING A SACRIFICIAL CONDUCTIVE STACK TO PREVENT CORROSION
    6.
    发明申请
    METHOD OF USING A SACRIFICIAL CONDUCTIVE STACK TO PREVENT CORROSION 审中-公开

    公开(公告)号：US20200058547A1

    公开(公告)日：2020-02-20

    申请号：US16661782

    申请日：2019-10-23

    Applicant: Texas Instruments Incorporated

    Inventor： Manoj K. Jain

    IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/00 ,  H01L23/532

    Abstract: A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 Å and 500 Å. The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat.

    REDUCED ESR IN TRENCH CAPACITOR
    10.
    发明申请
    REDUCED ESR IN TRENCH CAPACITOR 有权

    公开(公告)号：US20220406885A1

    公开(公告)日：2022-12-22

    申请号：US17489199

    申请日：2021-09-29

    Applicant: Texas Instruments Incorporated

    Inventor： Jing Hu ,  Zhi Peng Feng ,  Chao Zuo ,  Dongsheng Liu ,  Yunlong Liu ,  Manoj K. Jain ,  Shengpin Yang

    IPC: H01L49/02

    Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

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