公开(公告)号：US20230216528A1

公开(公告)日：2023-07-06

申请号：US17566047

申请日：2021-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Pranav SINHA ,  Mayank Kumar SINGH ,  Rittu SACHDEV ,  Karan Singh BHATIA ,  Shailesh JOSHI ,  Indu PRATHAPAN

IPC: H04B1/00 ,  H04B1/10 ,  H04B1/04 ,  H04B1/69

CPC classification number: H04B1/0075 ,  H04B1/1036 ,  H04B1/04 ,  H04B1/69 ,  H04B2001/6912 ,  H04B2001/0408 ,  H04B2001/1063 ,  H04B2001/1045

Abstract: A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.

公开(公告)号：US20220156044A1

公开(公告)日：2022-05-19

申请号：US17351699

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj GUPTA ,  Karthik SUBBURAJ ,  Sujaata RAMALINGAM ,  Karthik RAMASUBRAMANIAN ,  Indu PRATHAPAN

IPC: G06F7/49 ,  G06F7/501 ,  G06F9/355 ,  G06F17/14 ,  G06F16/901

Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

公开(公告)号：US20220120884A1

公开(公告)日：2022-04-21

申请号：US17351654

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Karthik RAMASUBRAMANIAN ,  Shailesh JOSHI ,  Kameswaran VENGATTARAMANE ,  Indu PRATHAPAN

IPC: G01S13/04 ,  G01S7/35 ,  G06F17/14 ,  G06F16/22 ,  G06F16/901

Abstract: A system includes a memory configured to store a two-dimensional data structure that includes radar data arranged such that radar data of a first transmitter is separated from radar data of a second transmitter by a Doppler offset in the two-dimensional data structure. The system also includes a data fetch mechanism that includes a lookup table (LUT) applied on either of two dimensions. The lookup table is configured to store a data fetch location in the two-dimensional data structure, where the data fetch location indicates a location from which to fetch a subset of the radar data from the two-dimensional data structure and the data fetch mechanism is configured to fetch the subset of the radar data from the two-dimensional data structure based on the LUT. The system includes a processor configured to perform a fast Fourier transform (FFT) on the fetched subset of the radar data.

公开(公告)号：US20240305321A1

公开(公告)日：2024-09-12

申请号：US18668397

申请日：2024-05-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Pranav SINHA ,  Mayank Kumar SINGH ,  Rittu SACHDEV ,  Karan Singh BHATIA ,  Shailesh JOSHI ,  Indu PRATHAPAN

IPC: H04B1/00 ,  H04B1/04 ,  H04B1/10 ,  H04B1/69

CPC classification number: H04B1/0075 ,  H04B1/04 ,  H04B1/1036 ,  H04B1/69 ,  H04B2001/0408 ,  H04B2001/1045 ,  H04B2001/1063 ,  H04B2001/6912

Abstract: In a radar system, an intermediate frequency amplifier (IFA) is configured with two high-pass filter stages, each having an amplifier and a configurable impedance component. A control signal is activated as the radar system begins to transmit a chirp signal to lower the impedance of the configurable impedance components during an initial portion of the chirp transmission to achieve faster settling of the IFA output signal. After the initial portion, the control signal deactivates while transmission of the chirp continues to increase the impedance of the configurable impedance components to a level sufficient to effectively perform filtering of unwanted signals received by the radar system.

公开(公告)号：US20240288563A1

公开(公告)日：2024-08-29

申请号：US18654683

申请日：2024-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik SUBBURAJ ,  Karthik RAMASUBRAMANIAN ,  Shailesh JOSHI ,  Kameswaran VENGATTARAMANE ,  Indu PRATHAPAN

IPC: G01S13/04 ,  G01S7/35 ,  G06F16/22 ,  G06F16/901 ,  G06F17/14

CPC classification number: G01S13/04 ,  G01S7/35 ,  G06F16/2264 ,  G06F16/9017 ,  G06F17/142

Abstract: Systems and instruction carrying non-transitory processor-readable mediums are provided to facilitate access of radar data that may be scattered or non-uniformly located within a region of memory for further processing of such radar data. An example system includes counters that increment on different dimensions of the memory region, a lookup table, multipliers, an adder, and a wraparound mechanism to access different sets of non-contiguously stored radar data from a region of memory. The wraparound mechanism performs a wraparound operation when a combined address, generated by the adder based on addresses obtained by the multipliers, is greater than a last valid address in the region. The wraparound operation generates a new combined address that is used to fetch data from the memory. A transform operation is then performed on the fetched data.

公开(公告)号：US20220155368A1

公开(公告)日：2022-05-19

申请号：US17351750

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujaata RAMALINGAM ,  Karthik SUBBURAJ ,  Pankaj GUPTA ,  Anil Varghese MANI ,  Karthik RAMASUBRAMANIAN ,  Indu PRATHAPAN

IPC: G01R31/317 ,  G01R29/26 ,  G11C19/28 ,  G01S7/40

Abstract: A system includes a shift register to store data samples, where the shift register includes a cell under test (CUT), a left guard cell, a right guard cell, a left window, and a right window. The system includes two sets of comparators to compare incoming data samples with data samples in the left window and the right window to compute ranks of the incoming data samples. The system includes a sorted index array to store a rank of the data samples in the shift register. The system includes a selector to select a Kth smallest index from the sorted index array and its corresponding data sample from the shift register. The system includes a target comparator, where the first comparator input receives a data sample from the CUT and the second comparator input receives a Kth smallest data sample, and the comparator output indicates a CFAR target detection.

公开(公告)号：US20240345805A1

公开(公告)日：2024-10-17

申请号：US18753107

申请日：2024-06-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj GUPTA ,  Karthik SUBBURAJ ,  Sujaata RAMALINGAM ,  Karthik RAMASUBRAMANIAN ,  Indu PRATHAPAN

IPC: G06F7/49 ,  G06F7/501 ,  G06F17/14

CPC classification number: G06F7/49 ,  G06F7/501 ,  G06F17/142

Abstract: A system includes Radix-22 butterfly stages, each including first and second Radix-22 butterfly circuits, in which the first Radix-22 butterfly circuit of a first Radix-22 butterfly stage includes a data input coupled to a system data input, and one of the first Radix-22 butterfly circuit and the second Radix-22 butterfly circuit of a last Radix-22 butterfly stage includes a data output coupled to a system data output. The system further includes a Radix-3 butterfly circuit including a data input coupled to the system data input and a data output selectively couplable to a data input of one of the first or second Radix-22 butterfly circuits of a second or later Radix-22 butterfly stage based on a particular point transform to be performed by the system. A set of memories are used by either the first Radix-22 butterfly stage or the Radix-3 butterfly circuit, depending on the particular point transform.

公开(公告)号：US20230385369A1

公开(公告)日：2023-11-30

申请号：US18447029

申请日：2023-08-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu PRATHAPAN ,  Sai Ram Prakash JAYANTHI

IPC: G06F17/14 ,  G06F13/28 ,  G06F7/76

CPC classification number: G06F17/142 ,  G06F13/287 ,  G06F7/768

Abstract: A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.

公开(公告)号：US20220091928A1

公开(公告)日：2022-03-24

申请号：US17027888

申请日：2020-09-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Desmond FERNANDES ,  Indu PRATHAPAN ,  Jasbir SINGH ,  Prathap SRINIVASAN ,  Rishav KARKI

IPC: G06F11/10 ,  G06F11/07 ,  G06F13/40

Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.

公开(公告)号：US20210279298A1

公开(公告)日：2021-09-09

申请号：US17331215

申请日：2021-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu PRATHAPAN ,  Sai Ram Prakash JAYANTHI

IPC: G06F17/14 ,  G06F7/76 ,  G06F13/28

Abstract: A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.