公开(公告)号：US10200052B2

公开(公告)日：2019-02-05

申请号：US15859437

申请日：2017-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Neeraj Shrivastava ,  Jafar Sadique Kaviladath

IPC: H03M1/12 ,  H03M1/00 ,  H03M1/14 ,  H03M1/16

Abstract: In some examples, a system comprises an analog-to-digital converter (ADC) to receive an analog input signal and a reset signal, the ADC to convert the analog input signal into a digital signal. The system comprises a digital-to-analog converter (DAC), coupled to the ADC, to convert the digital signal into an internal analog signal. The system includes a first capacitor, coupled to the DAC, to receive the internal analog signal. The system comprises a first switch, coupled to the first capacitor, to provide the analog input signal to the first capacitor. The system comprises a second switch to couple the first capacitor to ground.

公开(公告)号：US10181861B1

公开(公告)日：2019-01-15

申请号：US15883623

申请日：2018-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jafar Sadique Kaviladath ,  Neeraj Shrivastava

IPC: H03M1/36 ,  H03K19/0175

Abstract: A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.

公开(公告)号：US09548752B1

公开(公告)日：2017-01-17

申请号：US15048027

申请日：2016-02-19

Applicant: Texas Instruments Incorporated

Inventor： Neeraj Shrivastava ,  Supreet Joshi ,  Himanshu Varshney ,  Jafar Sadique Kaviladath ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: H03M1/66 ,  H03M1/10 ,  H03M1/78 ,  H03M1/74

CPC classification number: H03M1/1009 ,  H03M1/1019 ,  H03M1/1057 ,  H03M1/66 ,  H03M1/742 ,  H03M1/745 ,  H03M1/785

Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

Abstract translation: 本公开提供了包括多个DAC元件的电流转向数模转换器（DAC）。 多个DAC元件中的至少一个DAC元件耦合到校准电路。 校准电路包括通过第一估计开关耦合到DAC元件的主节点的固定电流源。 数字码发生器耦合到主节点，并且产生对应于在主节点处产生的主电压的第一数字码。 数字代码生成器产生第二数字代码。 校正DAC耦合到数字代码发生器并且基于第二数字代码产生偏置电压。 偏置电压被提供给DAC元件，使得流过多个DAC元件中的每个DAC元件的电流相等。

公开(公告)号：US11329661B1

公开(公告)日：2022-05-10

申请号：US17391516

申请日：2021-08-02

Applicant: Texas Instruments Incorporated

Inventor： Jafar Sadique Kaviladath

IPC: H03M1/66 ,  H03M1/12 ,  H03M1/10 ,  H03M1/06

Abstract: A buffer circuit includes a first differential signal input, a second differential signal input, a first source follower circuit, and a second source follower circuit. The first source follower circuit includes a first signal output, and a first input transistor. The first input transistor is coupled to the first differential signal input, and is configured to drive the first signal output. The second source follower circuit includes a second signal output, a second input transistor, and a cascode transistor. The second input transistor is coupled to the second differential signal input, and is configured to drive the second signal output. The cascode transistor is coupled to the second input transistor and the first signal output, and is configured to compensate for non-linearity of the second input transistor based on an output signal provided at the first signal output.

公开(公告)号：US10396814B2

公开(公告)日：2019-08-27

申请号：US16211259

申请日：2018-12-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jafar Sadique Kaviladath ,  Neeraj Shrivastava

IPC: H03M1/36 ,  H03K19/0175

Abstract: A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.