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公开(公告)号：US20220116030A1
公开(公告)日：2022-04-14
申请号：US17558794
申请日：2021-12-22
IPC分类号： H03K5/1252 , G11C19/28 , G06F1/10 , G06F1/08 , H03K19/21
摘要： A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.
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公开(公告)号：US20190175037A1
公开(公告)日：2019-06-13
申请号：US15835646
申请日：2017-12-08
IPC分类号： A61B5/024
摘要： An apparatus to detect a heart rate of a user includes a motion detection circuit configured to generate a motion status signal indicative of a motion status of the user. The apparatus also comprises a filter circuit coupled to the motion detection circuit that is configured to generate a filter circuit output signal based on dynamically variable. The coefficients are dependent on the motion status signal and a first signal received by the filter circuit. The apparatus also comprises a combination circuit coupled to the filter circuit and configured to receive a second signal indicative of the ambient light, the motion of the user, and non-ambient light reflected from the user. The combination circuit is configured to determine a difference between the second signal and the filter circuit output signal to generate a combination circuit output signal.
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公开(公告)号：US20170078970A1
公开(公告)日：2017-03-16
申请号：US14852234
申请日：2015-09-11
IPC分类号： H04W52/02 , H04L27/227 , H04W24/08 , H04B1/16
CPC分类号： H04W52/0232 , H04B1/16 , H04L27/2656 , H04L27/2663 , H04W52/0229 , H04W84/12 , Y02D70/142 , Y02D70/144
摘要： The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.
摘要翻译： 本公开提供了一种低功率接收机。 接收机包括接收RF信号并产生输入信号的第一信道。 接收机还包括第二信道和分组检测电路。 分组检测电路耦合到第一信道和第二信道。 分组检测电路检测输入信号中的有效分组，并且在检测到有效分组时激活第二信道。
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公开(公告)号：US20220066975A1
公开(公告)日：2022-03-03
申请号：US17364672
申请日：2021-06-30
发明人： Aravind GANESAN , Nagalinga Swamy Basayya AREMALLAPUR , Jaiganesh BALAKRISHNAN , Robert Clair KELLER
摘要： A circuit includes: a parallel data interface; and transition control circuitry coupled to the parallel data interface. The transition control circuitry is configured to: receive an input bit stream sample; determine a bit transformation pattern for the input bit stream sample in accordance with a target criteria; and generate an output bit stream symbol from the input bit stream sample and the bit transformation pattern, wherein the output bit stream symbol has more bits than the input bit stream sample.
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公开(公告)号：US20210391944A1
公开(公告)日：2021-12-16
申请号：US17462055
申请日：2021-08-31
发明人： Sanjay PENNAM , Vamsi Krishna KANDALLA , Brahmendra Reddy YATHAM , Shailesh WARDHEN , Jaiganesh BALAKRISHNAN , Jawaharlal TANGUDU
摘要： A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.
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公开(公告)号：US20210119622A1
公开(公告)日：2021-04-22
申请号：US17071302
申请日：2020-10-15
摘要： A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.
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7.发明申请公开(公告)号：US20190178993A1
公开(公告)日：2019-06-13
申请号：US15834178
申请日：2017-12-07
摘要： A three dimensional time of flight (TOF) camera includes a transmitter and a receiver. The transmitter is configured to generate an electrical transmit signal at a plurality of frequencies over an integration time period and generate a transmit optical waveform corresponding with the electrical transmit signal. The receiver is configured to receive a reflected optical waveform that is the transmit optical waveform reflected off of an object, integrate the reflected optical waveform over the integration time period, and determine a distance to the target object based on a TOF of the optical waveform. The integration time period includes exposure time periods. A length of each of the exposure time periods corresponds to one of the frequencies. The TOF is determined based on a correlation of the electrical transmit signal and the return optical waveform utilizing a correlation function with respect to the integration time period.
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公开(公告)号：US20170324423A1
公开(公告)日：2017-11-09
申请号：US15392491
申请日：2016-12-28
CPC分类号： H03M7/6047 , H03D7/165 , H03D2200/0056 , H03H17/0664 , H03M7/3059
摘要： A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.
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公开(公告)号：US20220173947A1
公开(公告)日：2022-06-02
申请号：US17538460
申请日：2021-11-30
IPC分类号： H04L27/14
摘要： A digital down converter (DDC) that improves efficiency by taking advantage of the periodicity of the coarse mixing process and the memory inherent in the convolution operation performed by decimation filters. In embodiments, the DDC filters and decimates a received signal to generate subfilter outputs and coarse mixes the subfilter outputs for each frequency band of interest. Accordingly, the DDC eliminates the need for separate decimation filters for each of the in-phase (I-phase) and quadrature (Q-phase) signals of each frequency band. In some embodiments, for each frequency band, the DDC combines the subfilter outputs into partial sums for each of the I- and Q-phases. In some of those embodiments, the coarse mixing operation is performed by multiplying the partial sums by real multiplicands and performing a simple post-rotation operation. In those embodiments, the DDC significantly reduces the number of multiplication operations required to perform the coarse mixing process.
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公开(公告)号：US20210176005A1
公开(公告)日：2021-06-10
申请号：US16936065
申请日：2020-07-22
发明人： Sanjay PENNAM , Vamsi Krishna KANDALLA , Brahmendra Reddy YATHAM , Shailesh WARDHEN , Jaiganesh BALAKRISHNAN , Jawaharlal TANGUDU
摘要： A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.
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