公开(公告)号：US20250087583A1

公开(公告)日：2025-03-13

申请号：US18958537

申请日：2024-11-25

Applicant: Texas Instruments Incorporated

Inventor： Ujwal RADHAKRISHNA ,  Vinod RAI ,  Yogesh RAMADASS ,  Anant KAMATH ,  Kashyap BAROT

IPC: H01L23/525 ,  H02H3/04

Abstract: A device includes first and second device terminals, a fuse, a first circuit, a first transistor, and a control circuit. The fuse terminal couples to the first device terminal. The first circuit couples to the second fuse terminal. The second fuse terminal has a first voltage. The first transistor has a first control input and first and second current terminals. The first current terminal couples to the second fuse terminal, and the second current terminal couples to the second device terminal. The control circuit: turns “on” the first transistor into a saturation region if the first voltage exceeds a threshold and a current through the fuse exceeds a trip threshold current of the fuse; and turns “on” the first transistor into a linear region if the first voltage exceeds a threshold and a current through the fuse is below the trip threshold current of the fuse.

公开(公告)号：US20250076348A1

公开(公告)日：2025-03-06

申请号：US18524737

申请日：2023-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kashyap BAROT ,  Arvind GUPTA ,  Avinash SHAH ,  Sreeram Nasum S

IPC: G01R19/00

Abstract: An opto-emulator transmitter includes: a current controller; an oscillator circuit; and receiver replica circuitry. The current controller has a first terminal, a second terminal, and a third terminal. The oscillator circuit has a first terminal, a second terminal, and a third terminal. The first terminal of the oscillator circuit is coupled to the second terminal of the current controller. The receiver replica circuitry has a first terminal, a second terminal, and a third terminal. The first terminal of the receiver replica circuitry is coupled to the second terminal of the oscillator circuit. The second terminal of the receiver replica circuitry is coupled to the third terminal of the oscillator circuit. The third terminal of the receiver replica circuitry is coupled to the third terminal of the current controller.

公开(公告)号：US20250047199A1

公开(公告)日：2025-02-06

申请号：US18362040

申请日：2023-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arvind GUPTA ,  Kashyap BAROT ,  Sreeram Nasum S

IPC: H02M3/07

Abstract: A circuit includes a charge pump stage and a common-mode filter. The charge pump stage includes first and second transistors, and first and second capacitors. The second transistor has a first terminal coupled to a control terminal of the first transistor, has a second terminal, and has a control terminal coupled to a first terminal of the first transistor. The first capacitor is coupled between a second terminal of the first transistor and the control terminal of the first transistor. The second capacitor is coupled between the second terminal of the second transistor and the control terminal of the second transistor. The common-mode filter includes third and fourth capacitors. The third capacitor is coupled between the second terminal of the first transistor and the control terminal of the first transistor. The fourth capacitor is coupled between the third capacitor and the control terminal of the second transistor.

公开(公告)号：US20230268270A1

公开(公告)日：2023-08-24

申请号：US17677729

申请日：2022-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ujwal RADHAKRISHNA ,  Vinod RAI ,  Yogesh RAMADASS ,  Anant KAMATH ,  Kashyap BAROT

IPC: H01L23/525 ,  H02H3/04

CPC classification number: H01L23/5256 ,  H02H3/046

Abstract: A device includes first and second device terminals, a fuse, a first circuit, a first transistor, and a control circuit. The fuse terminal couples to the first device terminal. The first circuit couples to the second fuse terminal. The second fuse terminal has a first voltage. The first transistor has a first control input and first and second current terminals. The first current terminal couples to the second fuse terminal, and the second current terminal couples to the second device terminal. The control circuit: turns “on” the first transistor into a saturation region if the first voltage exceeds a threshold and a current through the fuse exceeds a trip threshold current of the fuse; and turns “on” the first transistor into a linear region if the first voltage exceeds a threshold and a current through the fuse is below the trip threshold current of the fuse.

公开(公告)号：US20240195412A1

公开(公告)日：2024-06-13

申请号：US18194289

申请日：2023-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kashyap BAROT ,  Kumar Anurag SHRIVASTAVA ,  Sreeram Nasum S

IPC: H03K17/687

CPC classification number: H03K17/6874

Abstract: A circuit includes a switch and a switch controller. The switch has a first terminal coupled to a voltage supply terminal, a second terminal coupled to a ground terminal and to a first bondwire terminal. The switch controller includes: a first resistor, a second resistor, a capacitor, and a buffer circuit. The first resistor has a first terminal coupled to a second bondwire terminal. The second resistor has a first terminal coupled to the voltage supply terminal and has a second terminal coupled to a second terminal of the first resistor. The capacitor has a first terminal coupled to the ground terminal and to the first bondwire terminal and has a second terminal coupled to second terminals of the first and second resistors. The buffer circuit has a terminal coupled to the second terminal of the capacitor and has an output terminal coupled to the control terminal of the switch.

公开(公告)号：US20240105382A1

公开(公告)日：2024-03-28

申请号：US17954735

申请日：2022-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kashyap BAROT ,  Sreeram S ,  Kumar Anurag SHRIVASTAVA ,  Viresh CHINCHANSURE

IPC: H01F27/30 ,  H01F27/32

CPC classification number: H01F27/303 ,  H01F27/306 ,  H01F27/324

Abstract: A transformer includes a substrate and a first metal layer having a first inductor having a first center tap. A second metal layer includes a second inductor having a second center tap, and the second metal layer includes a bond pad. A third metal layer includes a first conductor electrically connecting the bond pad to the first center tap, and the third metal layer includes a second conductor electrically connecting the bond pad and the first center tap. The third metal layer is situated between the substrate and the first metal layer, and the first metal layer is situated between the third metal layer and the second metal layer.

公开(公告)号：US20240195409A1

公开(公告)日：2024-06-13

申请号：US18194267

申请日：2023-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Avinash SHAH ,  Kashyap BAROT ,  Sreeram Nasum S

IPC: H03K17/687

CPC classification number: H03K17/6871

Abstract: A circuit incudes: a first transistor; a capacitor; a second transistor; and a second resistor. The first transistor has a current terminal and a first control terminal. The capacitor has a capacitor terminal coupled to the current terminal of the first transistor. The second transistor has a first current terminal, a second current terminal, and a second control terminal. The first current terminal of the second transistor is coupled to the capacitor terminal. The second current terminal of the second transistor is coupled to the first control terminal. The resistor has a resistor terminal coupled to the second control terminal.

公开(公告)号：US20200279602A1

公开(公告)日：2020-09-03

申请号：US16793447

申请日：2020-02-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreeram Subramanyam NASUM ,  Niranjan SHANKAR ,  Kumar Anurag SHRIVASTAVA ,  Kashyap BAROT

IPC: G11C11/406 ,  G11C11/409 ,  G11C7/22 ,  G11C7/10

Abstract: An encoding and transmitting system for a digital isolator system includes a transmitter for transmitting combined edge indicator signals through an isolation barrier, an encoder for generating the combined edge indicator signals based on first and second signals, a refresh clock generator for generating a refresh clock signal based on the first signal, and a refresh edge generator for masking at least a portion of the refresh clock signal, such that the portion of the refresh clock signal is not reflected in the second signal. The isolation barrier of the digital isolator system may be a capacitive isolation barrier for galvanically isolating a receiver from the transmitter. If desired, the refresh edge generator may include a refresh mask generator, one or more logic gates, and a glitch filter. A method of operating a digital isolator system is also described.