公开(公告)号：US11626879B2

公开(公告)日：2023-04-11

申请号：US17463115

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan Subbannavar ,  Rakesh Dimri ,  Somasekar J ,  Mohammad Asif Farooqui

IPC: H03K19/08

Abstract: An integrated circuit, and method of forming the same. The integrated circuit includes standard logic cells and a combined logic cell over a semiconductor substrate. Each standard logic cell includes a standard height, a width that is an integer multiple of a unit width, first and second power rails, and at least one transistor and interconnections configured to implement a logic function that produces a single logic output. The combined logic cell includes the standard height, a width that is an integer multiple of the unit width, the first and second power rails, and at least two transistors and interconnections configured to implement a first logic function and a second logic function. The first and second logic functions produce first and second logic outputs, respectively. The interconnections are configured to direct the first logic output and the second logic output to destinations outside the combined logic cell.

公开(公告)号：US20240201997A1

公开(公告)日：2024-06-20

申请号：US18068030

申请日：2022-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Mody ,  Kedar Chitnis ,  Prithvi Shankar Yeyyadi Anantha ,  Shailesh Ghotgalkar ,  Donald Steiss ,  Mohammad Asif Farooqui ,  Nikhil Sangani ,  Sriraj Chellappan

IPC: G06F9/345 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F9/345 ,  G06F9/30021 ,  G06F9/3877 ,  G06F9/5016 ,  G06F9/5027

Abstract: Various embodiments disclosed herein relate to compute offloading by supplying operands to hardware accelerators from central processing units. An example embodiment includes a system configured to perform compute offloading. The system comprises a processing unit configured to write data to a memory and a memory adaptor bridge coupled between the processing unit and the memory. The memory adaptor bridge is configured to, in response to an attempt by the processing unit to write an operand to a memory location mapped to a function of a hardware accelerator, write the operand to a different memory location accessible by the hardware accelerator. The memory adaptor bridge is further configured to obtain a result of the function performed on the operand by the hardware accelerator and provide the result of the function to a memory location accessible by the processing unit.

公开(公告)号：US20250103244A1

公开(公告)日：2025-03-27

申请号：US18371338

申请日：2023-09-21

Applicant: Texas Instruments Incorporated

Inventor： Vignesh Raghavendra ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Sai Karthik Rajaraman ,  Shailesh Ganapat Ghotgalkar ,  Mohammad Asif Farooqui

IPC: G06F3/06

Abstract: An example apparatus includes a read queue to store a first read request to access a first storage, sequencing circuitry coupled to the read queue, and prioritization circuitry coupled to the sequencing circuitry and coupled to the first storage and a second storage via a shared bus. The example sequencing circuitry is to sequence a portion of a second request to access the second storage to be interleaved with a wait interval of the first read request, the second request queued after the first read request. Additionally, the example prioritization circuitry is to generate a first transaction to access the first storage over the shared bus and a second transaction to access the second storage over the shared bus concurrently with the first transaction, the first transaction based on the first read request, the second transaction based on the second request.

公开(公告)号：US20250036315A1

公开(公告)日：2025-01-30

申请号：US18359729

申请日：2023-07-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Vignesh Raghavendra ,  Mihir Mody ,  Mohammad Asif Farooqui ,  Shailesh Ghotgalkar ,  Sai Rajaraman

IPC: G06F3/06

Abstract: Various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. In an example embodiment, a system is provided. The system includes memory access circuitry and processing circuitry coupled to the memory access circuitry. The memory access circuitry is configured to receive a read request corresponding to a set of instructions for execution by processing circuitry stored in non-volatile memory, determine whether to preempt current access to the non-volatile memory corresponding to one or more access requests in favor of the read request based on a priority of the read request relative to the one or more access requests, obtain the set of instructions from the non-volatile memory, and supply the set of instructions to the processing circuitry. The processing circuitry executes the set of instructions.

公开(公告)号：US20230061062A1

公开(公告)日：2023-03-02

申请号：US17463115

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan Subbannavar ,  Rakesh Dimri ,  Somasekar J ,  Mohammad Asif Farooqui

IPC: H03K19/08

Abstract: An integrated circuit, and method of forming the same. The integrated circuit includes standard logic cells and a combined logic cell over a semiconductor substrate. Each standard logic cell includes a standard height, a width that is an integer multiple of a unit width, first and second power rails, and at least one transistor and interconnections configured to implement a logic function that produces a single logic output. The combined logic cell includes the standard height, a width that is an integer multiple of the unit width, the first and second power rails, and at least two transistors and interconnections configured to implement a first logic function and a second logic function. The first and second logic functions produce first and second logic outputs, respectively. The interconnections are configured to direct the first logic output and the second logic output to destinations outside the combined logic cell.