MULTIPHASE CONTROLLER COMMUNICATION
    2.
    发明公开

    公开(公告)号:US20230170796A1

    公开(公告)日:2023-06-01

    申请号:US17537595

    申请日:2021-11-30

    CPC classification number: H02M3/155 H02M1/08 H02M1/32

    Abstract: A multiphase controller includes an integrator enable terminal, a pulse width modulator, an error integrator, an open drain driver, and an integrator enable circuit. The integrator enable terminal is adapted to be coupled to the integrator enable terminal of a different instance of the multiphase controller. The pulse width modulator is configured to modulate a power stage. The error integrator is configured to control the pulse width modulator. The open drain driver is coupled to the integrator enable circuit. The integrator enable circuit is coupled to the pulse width modulator, the error integrator, the open drain driver, and the integrator enable terminal. The integrator enable circuit is configured to activate the open drain driver responsive to generation of a power stage control pulse by the pulse width modulator, and activate the error integrator responsive to a logic low signal at the integrator enable terminal.

    VOLTAGE IDENTIFICATION SIGNAL DECODER WITH PRECHARGING

    公开(公告)号:US20240214002A1

    公开(公告)日:2024-06-27

    申请号:US18086204

    申请日:2022-12-21

    CPC classification number: H03M1/822 H03M1/0626 H03M1/1205

    Abstract: In an example, an apparatus includes a first decoder circuit having a first voltage identification (VID) analog input and a first digital output. The apparatus also includes a precharge circuit having a digital input and a first analog output, the digital input coupled to the first digital output. The apparatus also includes a second decoder circuit having a second VID analog input, a precharge analog input and a second digital output, the precharge analog input coupled to the first digital output. The apparatus also includes a multiplexer having a multiplexer output and first and second multiplexer inputs, the first multiplexer input coupled to the first digital output, and the second multiplexer input coupled to the second digital output.

    CURRENT SHARING POWER STAGE FOR PHASE MULTIPLICATION APPLICATIONS

    公开(公告)号:US20220393464A1

    公开(公告)日:2022-12-08

    申请号:US17339576

    申请日:2021-06-04

    Abstract: A system includes a first power stage circuit having a first PWM input, a first voltage input and a first power output. The first power stage circuit is configured to provide a first current at the first power output responsive to a PWM signal at the first PWM input, and configured to receive a voltage at the first voltage input. The system includes a second power stage circuit having a second PWM input, a second voltage input and a second power output. The second voltage input is coupled to the first voltage input, and the second power stage circuit is configured to provide a second current at the second power output responsive to the PWM signal at the second PWM input. The second power stage circuit is configured to receive the voltage at the second voltage input, the voltage representing an average of the first current and the second current.

    AMPLIFIER CAPACITIVE LOAD COMPENSATION

    公开(公告)号:US20220149792A1

    公开(公告)日:2022-05-12

    申请号:US17514087

    申请日:2021-10-29

    Abstract: An amplifier includes a first stage and a second stage. The first stage is configured to amplify a received signal. The second stage is coupled to the first stage. The second stage includes a source follower and a compensation network. The source follower includes an input and an output. The compensation network is coupled to the input of the source follower and the output of the source follower. The compensation network is configured to modify a magnitude and phase response of the first stage based on a load capacitance coupled to the output of the source follower.

    PINSTRAP DETECTION CIRCUIT
    7.
    发明申请

    公开(公告)号:US20210203346A1

    公开(公告)日:2021-07-01

    申请号:US16732213

    申请日:2019-12-31

    Abstract: In at least some examples, an integrated circuit includes an input pin and an analog-to-digital converter (ADC) comprising an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit comprising an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistance circuit. In an example, the resistance circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.

    RDSON-BASED CURRENT SENSING SYSTEM
    10.
    发明申请

    公开(公告)号:US20220271664A1

    公开(公告)日:2022-08-25

    申请号:US17678220

    申请日:2022-02-23

    Abstract: A device includes a current mirror, a switch, first and second current paths, first and second buffers, a variable resistor, a temperature-sensing circuit, and a controller. The first current path is coupled between the current mirror's input and the switch. The switch switches between ground and a transistor based on a control signal. The second current path is coupled between a first current mirror output and ground. The first buffer is coupled to a second current mirror output. The second buffer is coupled to the variable resistor, which is coupled to the first buffer. The temperature-sensing circuit provides a device temperature to the controller, which is coupled to a first buffer output and determines a first adjustment to the first and second current paths and a second adjustment to the variable resistor based on the device temperature.

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