-
公开(公告)号:US20220224868A1
公开(公告)日:2022-07-14
申请号:US17146363
申请日:2021-01-11
Applicant: Texas Instruments Incorporated
Inventor: Noah Alan Robb , Harsh Dinesh Jhaveri , Priyankar Mathuria
IPC: H04N9/31 , B81B7/02 , G11C11/413 , G11C5/06 , G02B26/08
Abstract: In a described example, a device includes: a semiconductor substrate; a memory array on the semiconductor substrate, the memory array comprising rows and columns of memory cells in a Manhattan pattern, the memory cells having a pitch in a direction along the columns; and an array of micromirrors in a diamond pattern over the memory cells, the micromirrors coupled to corresponding memory cells, the micromirrors having a diagonal pitch length in the direction along the columns that is between 1.8 times the pitch and 2.2 times the pitch.
-
公开(公告)号:US11997430B2
公开(公告)日:2024-05-28
申请号:US17146363
申请日:2021-01-11
Applicant: Texas Instruments Incorporated
Inventor: Noah Alan Robb , Harsh Dinesh Jhaveri , Priyankar Mathuria
CPC classification number: H04N9/312 , B81B7/02 , G02B26/0816 , G02B26/0833 , G02B26/105 , G11C5/063 , G11C11/413 , H04N9/3152 , B81B2201/042 , B81B2201/07
Abstract: In a described example, a device includes: a semiconductor substrate; a memory array on the semiconductor substrate, the memory array comprising rows and columns of memory cells in a Manhattan pattern, the memory cells having a pitch in a direction along the columns; and an array of micromirrors in a diamond pattern over the memory cells, the micromirrors coupled to corresponding memory cells, the micromirrors having a diagonal pitch length in the direction along the columns that is between 1.8 times the pitch and 2.2 times the pitch.
-
公开(公告)号:US10454457B1
公开(公告)日:2019-10-22
申请号:US16010696
申请日:2018-06-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Priyankar Mathuria
IPC: H03K3/00 , H03K3/037 , G01R31/3185 , H03K3/012 , H03K19/21
Abstract: A self-gating flip-flop circuit includes a flip-flop circuit and a clock circuit. The flip-flop circuit includes a clock input. The clock circuit is coupled to the clock input. The clock circuit includes a latch circuit, a reset circuit, and a gate circuit. The reset circuit is coupled to the latch circuit. The gate circuit is coupled to the latch circuit and the clock input.
-
-