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公开(公告)号：US20250076915A1
公开(公告)日：2025-03-06
申请号：US18951812
申请日：2024-11-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajat Chauhan , Divya Kaur
Abstract: In described examples, a circuit includes a current mirror circuit. A first stage is coupled to the current mirror circuit. A second stage is coupled to the current mirror circuit and to the first stage. A voltage divider network is coupled to the second stage. The circuit includes an output transistor having first and second terminals, in which the first terminal of the output transistor is coupled to the first stage, and the second terminal of the output transistor is coupled to the voltage divider network.
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公开(公告)号：US12181905B2
公开(公告)日：2024-12-31
申请号：US17682811
申请日：2022-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajat Chauhan , Divya Kaur
Abstract: In described examples, a circuit includes a current mirror circuit. A first stage is coupled to the current mirror circuit. A second stage is coupled to the current mirror circuit and to the first stage. A voltage divider network is coupled to the second stage. The circuit includes an output transistor having first and second terminals, in which the first terminal of the output transistor is coupled to the first stage, and the second terminal of the output transistor is coupled to the voltage divider network.
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公开(公告)号：US11598795B1
公开(公告)日：2023-03-07
申请号：US17464261
申请日：2021-09-01
Applicant: Texas Instruments Incorporated
Inventor： Rajat Chauhan , Sandeep Shylaja Krishnan , Joseph Alan Sankman
Abstract: In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (RDEGEN) of a differential amplifier stage of the circuit; and trimming a first resistor (R1) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R2) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (RPTAT) of the differential amplifier stage, a third resistor (R1PTAT) of the scaling amplifier stage, and a fourth resistor (R2PTAT) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.
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公开(公告)号：US11190105B1
公开(公告)日：2021-11-30
申请号：US17119862
申请日：2020-12-11
Applicant: Texas Instruments Incorporated
Inventor： Vipul Kumar Singhal , RR Manikandan , Rajat Chauhan , Vinod Joseph Menezes
Abstract: An electronic device having multiple power output circuits that individually include a switch control input, a bypass control input, an output transistor and an output control circuit that includes an RC circuit with a resistor and a capacitor coupled to the output transistor gate and a bypass switch in parallel with the RC circuit resistor. The electronic device includes a controller that selects one of the power output circuits for a given power transfer cycle, closes the bypass switch to bypass the resistor of the selected power output circuit and turns the output transistor of the selected power output circuit on to transfer current from the inductor to a load of the selected power output circuit.
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公开(公告)号：US11139807B2
公开(公告)日：2021-10-05
申请号：US16937712
申请日：2020-07-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajat Chauhan , Srikanth Srinivasan
IPC: H03K19/094 , G11C16/06 , G11C16/12 , H03K5/24 , H03K3/356
Abstract: A circuit that includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node.
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Patent Agency Ranking
公开(公告)号：US09240400B2
公开(公告)日：2016-01-19
申请号：US14043583
申请日：2013-10-01
Applicant: Texas Instruments Incorporated
Inventor： Venkateswara Reddy P , Vinayak Ghatawade , Rajat Chauhan
CPC classification number: H01L27/0248 , H01L27/0251 , H03K19/018592
Abstract: An input/output (IO) circuit is provided that reduces stress on a driver without using an additional reference voltage. The IO circuit receives an overshoot voltage and an undershoot voltage in a receive mode. The IO circuit includes a driver circuit. The driver circuit includes an NMOS transistor coupled to a PMOS transistor. A pad is coupled to the driver circuit. A PMOS protect circuit is coupled to the driver circuit and the pad. An NMOS protect circuit is coupled to the driver circuit and the pad. The NMOS protect circuit is configured to be activated only for a duration of the overshoot voltage received at the pad during the receive mode and the PMOS protect circuit is configured to be activated only for a duration of the undershoot voltage received at the pad during the receive mode.
Abstract translation: 提供了一种输入/输出（IO）电路，可以减少驱动器的压力，而不需要额外的参考电压。 IO电路在接收模式下接收过冲电压和下冲电压。 IO电路包括一个驱动电路。 驱动器电路包括耦合到PMOS晶体管的NMOS晶体管。 焊盘耦合到驱动器电路。 PMOS保护电路耦合到驱动器电路和焊盘。 NMOS保护电路耦合到驱动器电路和焊盘。 NMOS保护电路被配置为仅在接收模式期间仅在焊盘处接收到的过冲电压的持续时间被激活，并且PMOS保护电路被配置为仅在接收期间在焊盘处接收到的下冲电压的持续时间被激活 模式。
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公开(公告)号：US20220390975A1
公开(公告)日：2022-12-08
申请号：US17682335
申请日：2022-02-28
Applicant: Texas Instruments Incorporated
Inventor： Rajat Chauhan
IPC: G05F3/24
Abstract: Described embodiments include a circuit for controlling a voltage drop. The circuit includes a resistor coupled between an output voltage terminal and a reference voltage terminal. First, second and third switches each have respective first, second and third switch terminals. The respective second switch terminals are connected together and are coupled to the output voltage terminal. The respective third switch terminals are connected together and are coupled to the reference voltage terminal. A first transistor is coupled between a supply voltage terminal and the first switch. A second transistor is coupled between the supply voltage terminal and the second switch. A third transistor is coupled between the supply voltage terminal and the third switch. Control terminals of the first, second and third transistors are coupled to a gate control terminal.
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公开(公告)号：US10686437B2
公开(公告)日：2020-06-16
申请号：US16227636
申请日：2018-12-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rajat Chauhan
IPC: H03L7/00 , H03K17/081 , B60R16/03 , H02M7/06
Abstract: A circuit includes a first transistor including first and second current terminals. The first current terminal couples to a supply voltage node. A second transistor includes a second control input and third and fourth current terminals. The third current terminal couples to the second current terminal at an output node and the fourth current terminal couples to a ground node. A third transistor includes a third control input and fifth and sixth current terminals. The fifth current terminal couples to the output node and the sixth current terminal couples to the ground node. A fourth transistor includes a fourth control input and seventh and eighth current terminals. The eighth current terminal couples to the ground node and the seventh current terminal couples to the third control input. An inverter having an input coupled to the second control input and an output coupled to the fourth control input.
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公开(公告)号：US10601408B2
公开(公告)日：2020-03-24
申请号：US15952549
申请日：2018-04-13
Applicant: Texas Instruments Incorporated
Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.
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公开(公告)号：US20170149424A1
公开(公告)日：2017-05-25
申请号：US14951877
申请日：2015-11-25
Applicant: Texas Instruments Incorporated
Inventor： Rajat Chauhan , Keith Kunz
IPC: H03K5/24
CPC classification number: H03K5/249
Abstract: A comparator circuit comprising a first node operable to receive a voltage during a precharge phase and a second node operable to receive the voltage during the precharge phase. The comparator circuit also comprises a first selectable current path, comprising a first input transistor and a first programmable resistor, coupled to the first node and for selectively discharging the first node, and a second selectable current path, comprising a second input transistor and a second programmable resistor, coupled to the second node and for selectively discharging the second node, in complementary operation with respect to the first selectable current path. The comparator circuit also comprises circuitry for adjusting resistance of the first programmable resistor and the second programmable resistor in response to an offset between the first input transistor and the second input transistor.
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