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公开(公告)号：US20190028113A1
公开(公告)日：2019-01-24
申请号：US16139113
申请日：2018-09-24
Applicant: Texas Instruments Incorporated
Inventor： Rishi Soundararajan
Abstract: A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.
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公开(公告)号：US12191877B2
公开(公告)日：2025-01-07
申请号：US17898844
申请日：2022-08-30
Applicant: Texas Instruments Incorporated
Inventor： Sai Aditya Nurani , Rishi Soundararajan , Nithin Gopinath , Visvesvaraya Pentakota , Shagun Dusad
Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.
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公开(公告)号：US20240072820A1
公开(公告)日：2024-02-29
申请号：US17898844
申请日：2022-08-30
Applicant: Texas Instruments Incorporated
Inventor： Sai Aditya Nurani , Rishi Soundararajan , Nithin Gopinath , Visvesvaraya Pentakota , Shagun Dusad
CPC classification number: H03M1/1245 , H03M1/44 , H03M1/50 , H03M1/785
Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.
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公开(公告)号：US11088702B2
公开(公告)日：2021-08-10
申请号：US16856167
申请日：2020-04-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rishi Soundararajan , Visvesvaraya Pentakota
IPC: H03M1/20
Abstract: A method of converting an analog signal to a digital code, comprising: using a first comparator to receive an input signal and a first comparison signal, and to generate a first output as a function of the input signal and the first comparison signal; using a second comparator to receive the input signal and a second comparison signal, and to generate a second output as a function of the input signal and the second comparison signal; and using an interpolation comparator to receive the first and second outputs, and to generate a third output based on relative timing of the first and second outputs; further including multiplexing to permit a second-level comparator to receive timing signals from the interpolation comparator and only one of two dummy comparators.
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公开(公告)号：US10958258B2
公开(公告)日：2021-03-23
申请号：US16364239
申请日：2019-03-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rishi Soundararajan , Visvesvaraya Pentakota
Abstract: A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.
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Patent Agency Ranking
公开(公告)号：US10116321B2
公开(公告)日：2018-10-30
申请号：US15864090
申请日：2018-01-08
Applicant: Texas Instruments Incorporated
Inventor： Rishi Soundararajan
Abstract: A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.
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公开(公告)号：US20250096813A1
公开(公告)日：2025-03-20
申请号：US18966610
申请日：2024-12-03
Applicant: Texas Instruments Incorporated
Inventor： Sai Aditya Nurani , Rishi Soundararajan , Nithin Gopinath , Visvesvaraya Pentakota , Shagun Dusad
Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.
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公开(公告)号：US10284219B2
公开(公告)日：2019-05-07
申请号：US16139113
申请日：2018-09-24
Applicant: Texas Instruments Incorporated
Inventor： Rishi Soundararajan
Abstract: A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.
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公开(公告)号：US10284188B1
公开(公告)日：2019-05-07
申请号：US15945165
申请日：2018-04-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rishi Soundararajan , Visvesvaraya Pentakota
Abstract: A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.
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公开(公告)号：US20180131383A1
公开(公告)日：2018-05-10
申请号：US15864090
申请日：2018-01-08
Applicant: Texas Instruments Incorporated
Inventor： Rishi Soundararajan
CPC classification number: H03M1/46 , H03K5/2481 , H03M1/0607 , H03M1/36 , H03M1/44 , H03M1/48
Abstract: A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.
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