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    SYSTEM AND METHOD FOR IMPROVING EFFICIENCY FOR QUASI-SQUARE WAVE POWER CONVERTERS
    2.
    发明申请
    SYSTEM AND METHOD FOR IMPROVING EFFICIENCY FOR QUASI-SQUARE WAVE POWER CONVERTERS 有权

    公开(公告)号：US20170126122A1

    公开(公告)日：2017-05-04

    申请号：US14932705

    申请日：2015-11-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Monodeep KAR ,  Saurav BANDYOPADHYAY ,  Jeffrey MORRONI

    IPC: H02M3/158

    CPC classification number: H02M3/1588 ,  Y02B70/1466

    Abstract: A power converter includes a power stage having a switch-node of a switched-mode power supply that is coupled to an input voltage node by a power field-effect transistor (FET) to energize an inductive circuit and is coupled to a ground node by a synchronous rectifier in parallel with the inductive circuit. The power converter also includes a controller coupled to the power stage. The controller controls switching of the power FET and synchronous rectifier in a complimentary manner. The controller switches on the power FET during a first switching cycle. Subsequently, the controller switches on the synchronous rectifier and, in response to a current through the inductive circuit being approximately zero, switches off the synchronous rectifier. Subsequently, the controller switches on the synchronous rectifier again to generate a negative current through the inductive circuit prior to entering a second switching cycle.

    DELAY CORRECTION FOR ON-TIME GENERATOR CIRCUITRY
    3.
    发明公开
    DELAY CORRECTION FOR ON-TIME GENERATOR CIRCUITRY 审中-公开

    公开(公告)号：US20240275368A1

    公开(公告)日：2024-08-15

    申请号：US18169138

    申请日：2023-02-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Nilanjan PAL ,  Saurav BANDYOPADHYAY

    IPC: H03K5/01 ,  H03K5/24 ,  H03K17/56

    CPC classification number: H03K5/01 ,  H03K5/24 ,  H03K17/56 ,  H03K2005/00019

    Abstract: A circuit includes a comparator having first and second comparator inputs and a comparator output. A discharge switch is coupled between the first comparator input and a ground terminal. A capacitor has first and second capacitor terminals, in which the first capacitor terminal is coupled to the first comparator input. A delay correction circuit includes a sample-hold circuit coupled to the first capacitor terminal and the second capacitor terminal. An amplifier has a first amplifier input coupled to a hold output of the sample-hold circuit and a second amplifier input coupled to the second comparator input. A variable resistor is coupled between the second capacitor terminal and the ground terminal, and has a control input coupled to the amplifier output.

    LOAD RELEASE DETECTION CIRCUIT
    4.
    发明申请
    LOAD RELEASE DETECTION CIRCUIT 审中-公开

    公开(公告)号：US20200169159A1

    公开(公告)日：2020-05-28

    申请号：US16670768

    申请日：2019-10-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Saurav BANDYOPADHYAY ,  Thomas Matthew LaBELLA ,  Robert Allan NEIDORFF

    IPC: H02M1/08 ,  H03K5/24

    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first comparator, a second comparator, and a logic circuit. The first comparator includes a first input terminal coupled to a first node, a second input terminal coupled to a second node, and an output terminal. The second comparator includes a first input terminal coupled to the first node, a second input terminal coupled to a third node, and an output terminal. The logic circuit includes a first input terminal coupled to the output terminal of the first comparator, a second input terminal coupled to the output terminal of the second comparator, and an output terminal. The logic circuit is configured to determine a change in current over time based on analyzing an output signal of the first comparator and an output signal of the second comparator over a plurality of sequential cycles of operation.

    CURRENT SENSING WITH CAPACITIVE COMPENSATION
    6.
    发明申请
    CURRENT SENSING WITH CAPACITIVE COMPENSATION 有权

    公开(公告)号：US20220302837A1

    公开(公告)日：2022-09-22

    申请号：US17512842

    申请日：2021-10-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Song GUO ,  Saurav BANDYOPADHYAY

    IPC: H02M3/158 ,  H02M1/00

    Abstract: A current sense circuit includes a sense amplifier, a current mirror circuit, a resistor, a low-pass filter, and a capacitor. The sense amplifier is adapted to be coupled to a switching transistor of a DC-DC converter. The current mirror circuit is coupled to the sense amplifier, and is configured to generate a sense current proportional to a current flowing through the switching transistor. The resistor is coupled to the current mirror circuit, and is configured to generate a sense voltage based on the sense current. The low-pass filter is coupled to the resistor, and is configured to average the sense voltage over an averaging interval. The capacitor is coupled to the resistor, and is configured to store the sense voltage in a blanking interval that precedes the averaging interval, and provide a compensation current in the averaging interval.

    SEMICONDUCTOR PROCESS VARIATION DETECTOR
    7.
    发明申请
    SEMICONDUCTOR PROCESS VARIATION DETECTOR 有权

    公开(公告)号：US20210013805A1

    公开(公告)日：2021-01-14

    申请号：US16927558

    申请日：2020-07-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Robert Allan NEIDORFF ,  Saurav BANDYOPADHYAY ,  Ramanathan RAMANI

    IPC: H02M3/158 ,  H02M3/157 ,  H02M1/08

    Abstract: In some examples, a system includes a voltage source terminal, a voltage reference terminal, a field effect transistor (FET), a current source, a comparator, and adjustment circuitry. The FET has a gate terminal and a non-gate terminal, the gate terminal coupled to the voltage source terminal. The current source is coupled to the non-gate terminal. The comparator has a comparator output and first and second comparator inputs, the first comparator input coupled to the non-gate terminal, and the second comparator input coupled to the voltage reference terminal. The adjustment circuitry has a circuitry input and a circuitry output, the circuitry input coupled to the comparator output, and the adjustment circuitry configured to adjust the circuitry output responsive to the circuitry input, in which the adjustment reduces a drive strength of the circuit.

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