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公开(公告)号：US20240250715A1
公开(公告)日：2024-07-25
申请号：US18625353
申请日：2024-04-03
Applicant: Texas Instruments Incorporated
Inventor： Srijan Rastogi , Mayank Garg , Anant Shankar Kamath
CPC classification number: H04B3/36 , H03F3/45179
Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
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公开(公告)号：US11563462B1
公开(公告)日：2023-01-24
申请号：US17382499
申请日：2021-07-22
Applicant: Texas Instruments Incorporated
Inventor： Srijan Rastogi , Mayank Garg , Anant Shankar Kamath
Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
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3.发明授权公开(公告)号：US12136918B2
公开(公告)日：2024-11-05
申请号：US17872841
申请日：2022-07-25
Applicant: Texas Instruments Incorporated
Inventor： Srijan Rastogi , Sumantra Seth , Baher Haroun
Abstract: A driver system includes a non-inverting system input, an inverting system input, a non-inverting system output and an inverting system output. The driver system includes a line driver which includes a non-inverting driver input coupled to the non-inverting system input and includes an inverting driver input coupled to the inverting system input. The line driver includes an inverting driver output and a non-inverting driver output. The driver system includes a first termination resistor coupled between the non-inverting driver output and the non-inverting system output and includes a second termination resistor coupled between the inverting driver output and the inverting system output. The driver system includes a first amplifier stage coupled to the line driver and includes a second amplifier stage coupled to the line driver.
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公开(公告)号：US20230028275A1
公开(公告)日：2023-01-26
申请号：US17382499
申请日：2021-07-22
Applicant: Texas Instruments Incorporated
Inventor： Srijan Rastogi , Mayank Garg , Anant Shankar Kamath
Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
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公开(公告)号：US11984941B2
公开(公告)日：2024-05-14
申请号：US18100131
申请日：2023-01-23
Applicant: Texas Instruments Incorporated
Inventor： Srijan Rastogi , Mayank Garg , Anant Shankar Kamath
CPC classification number: H04B3/36 , H03F3/45179
Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
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Patent Agency Ranking
公开(公告)号：US20210119619A1
公开(公告)日：2021-04-22
申请号：US16905264
申请日：2020-06-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srijan Rastogi , Srikanth Manian
Abstract: A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.
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公开(公告)号：US11711072B2
公开(公告)日：2023-07-25
申请号：US16905264
申请日：2020-06-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srijan Rastogi , Srikanth Manian
CPC classification number: H03K5/01 , H03K3/037 , H03K19/20 , H03K2005/00019
Abstract: A serial bus re-driver circuit includes an edge detector circuit and a booster circuit. The edge detector circuit is configured to detect a transition of serial bus signal. The booster circuit is coupled to the edge detector circuit, and is configured to switch current to the serial bus signal. The booster circuit includes a leading edge boost pulse generation circuit and a trailing edge boost pulse generation circuit. The leading edge boost pulse generation circuit is configured to switch a first current pulse to the serial bus signal at the transition of the serial bus signal. The trailing edge boost pulse generation circuit is configured to switch a second current pulse to the serial bus signal. The second current pulse is shorter than the first current pulse.
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公开(公告)号：US20230155628A1
公开(公告)日：2023-05-18
申请号：US18100131
申请日：2023-01-23
Applicant: Texas Instruments Incorporated
Inventor： Srijan Rastogi , Mayank Garg , Anant Shankar Kamath
CPC classification number: H04B3/36 , H03F3/45179
Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
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公开(公告)号：US20220206983A1
公开(公告)日：2022-06-30
申请号：US17502418
申请日：2021-10-15
Applicant: Texas Instruments Incorporated
Inventor： Mustafa Ulvi Erdogan , Bharath Kumar Singareddy , Suzanne Mary Vining , Srijan Rastogi , Sirish Oruganti , Douglas Edward Wente
Abstract: A method of operating an embedded universal serial bus (eUSB) repeater includes holding an eUSB receiver and a USB transmitter in active states and holding a USB receiver and an eUSB transmitter in standby states. The method includes receiving by the eUSB receiver a token packet indicative of transmission of a first downstream packet, and transitioning the USB receiver and the eUSB transmitter from the standby states to the active states responsive to the token packet. The method includes transmitting the token packet by the USB transmitter. The method includes receiving by the eUSB receiver a downstream packet or receiving by the USB receiver an upstream packet within a first timeout period after receiving the token packet, and transmitting the downstream packet by the USB transmitter or transmitting the upstream packet by the eUSB transmitter.
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公开(公告)号：US20250021704A1
公开(公告)日：2025-01-16
申请号：US18523590
申请日：2023-11-29
Applicant: Texas Instruments Incorporated
Inventor： Win Naing Maung , Srijan Rastogi , Bharath Singareddy
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to prevent a false disconnection in universal serial bus devices. An example apparatus includes a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to a first connectional terminal, the second input terminal coupled to a second connection terminal; filter circuitry including an input terminal and an output terminal, the input terminal coupled to the output terminal of the comparator; a switch including a control terminal, a first current terminal, and a second current terminal, the control terminal coupled to the output terminal of the filter circuitry; and a current source including a first terminal and a second terminal, the first terminal coupled to at least one of the first connection terminal or the second connection terminal, the second terminal coupled to the first current terminal of the switch.
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