Valley current mode control for a voltage converter

    公开(公告)号:US11722061B2

    公开(公告)日:2023-08-08

    申请号:US17314710

    申请日:2021-05-07

    CPC classification number: H02M3/158 H02M1/08 H02M1/0003

    Abstract: A switching regulator includes a first transistor having a control input and the first transistor is coupled to an input voltage terminal. The regulator includes a second transistor having a control input. The second transistor is coupled to the first transistor at a switch terminal and to a ground terminal. The regulator also includes a controller coupled to the control inputs of the first and second transistor. The controller configured is configured to cause both the first and second transistors to be off concurrently during each of multiple switching cycles for an adaptive high impedance state. The length of time of the adaptive high impedance state is inversely related to current output by the switching regulator.

    Switch Mode Regulator With Slew Rate Control

    公开(公告)号:US20210184561A1

    公开(公告)日:2021-06-17

    申请号:US17114793

    申请日:2020-12-08

    Inventor: Tawen Mei

    Abstract: A circuit is configured to drive a switch mode regulator and to control the slew rate at a switching terminal of the regulator. The circuit includes first and second transistors coupled between a voltage supply terminal and a switching terminal, and includes third and fourth transistors coupled between the voltage supply terminal and the switching terminal. The circuit includes a fifth transistor coupled to the fourth transistor in a current mirror configuration and a sixth transistor coupled between the voltage supply terminal and the third transistor. The circuit includes a first resistor coupled between the voltage supply terminal and the fifth transistor, and includes a second resistor coupled between the sixth transistor and the second transistor.

    Low power switching mode regulator having automatic PFM and PWM operation
    3.
    发明授权
    Low power switching mode regulator having automatic PFM and PWM operation 有权
    低功耗开关模式调节器具有自动PFM和PWM操作

    公开(公告)号:US09287776B2

    公开(公告)日:2016-03-15

    申请号:US14333241

    申请日:2014-07-16

    Inventor: Tawen Mei

    CPC classification number: H02M3/156 H02M3/1563

    Abstract: A circuit and method for operating a switching mode power supply. A clock is driven by a current source to generate pulses at a fixed frequency using pulse width modulation for normal load demands. For light load demands, the current to the clock is reduced, and therefore the clock generates pulses at a lower, variable frequency and fixed duration using pulse frequency modulation. Thus, depending on the load condition, either fixed frequency pulses or fixed duration pulses are automatically provided to a power stage for conversion to an output voltage.

    Abstract translation: 一种用于操作开关模式电源的电路和方法。 时钟由电流源驱动,以便在正常负载需求下使用脉冲宽度调制以固定频率产生脉冲。 对于轻负载要求,时钟电流降低,因此时钟使用脉冲频率调制在较低,可变频率和固定持续时间内产生脉冲。 因此,根据负载条件,固定频率脉冲或固定持续时间脉冲自动提供给功率级以转换为输出电压。

    Recovery control for power converter

    公开(公告)号:US11722105B2

    公开(公告)日:2023-08-08

    申请号:US17498259

    申请日:2021-10-11

    Abstract: A device includes a first amplifier and a second amplifier. The first amplifier includes an inverting input configured to be coupled to a feedback node of an output of a power converter, a first non-inverting input configured to couple to a first voltage node, a second non-inverting input, and an output. The second amplifier includes an inverting input coupled to the output of the first amplifier, a non-inverting input coupled to a second voltage node, and an output. The device also includes a first transistor coupled to the output of the first amplifier and having a control terminal coupled to the output of the second amplifier, a capacitor coupled to a ground node and to the second non-inverting input of the first amplifier, and a current node coupled to the capacitor.

    MULTIPHASE SWITCHED MODE POWER SUPPLY CLOCKING CIRCUITS AND RELATED METHODS

    公开(公告)号:US20220131465A1

    公开(公告)日:2022-04-28

    申请号:US17572062

    申请日:2022-01-10

    Abstract: Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.

    Multiphase switched mode power supply clocking circuits and related methods

    公开(公告)号:US11251706B2

    公开(公告)日:2022-02-15

    申请号:US16413305

    申请日:2019-05-15

    Abstract: Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.

    Recovery control for power converter

    公开(公告)号:US11183977B2

    公开(公告)日:2021-11-23

    申请号:US16264311

    申请日:2019-01-31

    Abstract: A device includes a first amplifier and a second amplifier. The first amplifier includes an inverting input configured to be coupled to a feedback node of an output of a power converter, a first non-inverting input configured to couple to a first voltage node, a second non-inverting input, and an output. The second amplifier includes an inverting input coupled to the output of the first amplifier, a non-inverting input coupled to a second voltage node, and an output. The device also includes a first transistor coupled to the output of the first amplifier and having a control terminal coupled to the output of the second amplifier, a capacitor coupled to a ground node and to the second non-inverting input of the first amplifier, and a current node coupled to the capacitor.

    Mathematical function circuit
    9.
    发明授权

    公开(公告)号:US11152919B1

    公开(公告)日:2021-10-19

    申请号:US17138576

    申请日:2020-12-30

    Abstract: An example of an apparatus includes a bias circuit having first and second bias circuit outputs. The apparatus also includes a comparator having first and second comparator inputs. The apparatus also includes a first capacitor coupled between the second comparator input and the second bias circuit output. The apparatus also includes a first switch coupled between the second comparator input and the second bias circuit output. The apparatus also includes a second switch coupled between the first bias circuit output and an input terminal, a third switch coupled between the input terminal and the first comparator input, and a fourth switch coupled between the first bias circuit output and the first comparator input. The apparatus also includes a second capacitor coupled between the first comparator input and the second bias circuit output.

    Error amplifier with programmable on-chip and off-chip compensation

    公开(公告)号:US11616436B2

    公开(公告)日:2023-03-28

    申请号:US16782525

    申请日:2020-02-05

    Abstract: A system includes: an input voltage source; a power stage coupled to the input voltage source; a load coupled to an output of the power stage; and an error amplifier circuit coupled to the power stage. The error amplifier circuit includes an error amplifier; a transconductance stage coupled to an output of the error amplifier; an internal compensation switch; an external compensation switch; and control logic coupled to the internal compensation switch and the external compensation switch. The control logic is configured to selectively operate the internal compensation switch and the external compensation switch in one of an internal compensation mode and an external compensation mode.

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