Abstract:
A switching regulator includes a first transistor having a control input and the first transistor is coupled to an input voltage terminal. The regulator includes a second transistor having a control input. The second transistor is coupled to the first transistor at a switch terminal and to a ground terminal. The regulator also includes a controller coupled to the control inputs of the first and second transistor. The controller configured is configured to cause both the first and second transistors to be off concurrently during each of multiple switching cycles for an adaptive high impedance state. The length of time of the adaptive high impedance state is inversely related to current output by the switching regulator.
Abstract:
A circuit is configured to drive a switch mode regulator and to control the slew rate at a switching terminal of the regulator. The circuit includes first and second transistors coupled between a voltage supply terminal and a switching terminal, and includes third and fourth transistors coupled between the voltage supply terminal and the switching terminal. The circuit includes a fifth transistor coupled to the fourth transistor in a current mirror configuration and a sixth transistor coupled between the voltage supply terminal and the third transistor. The circuit includes a first resistor coupled between the voltage supply terminal and the fifth transistor, and includes a second resistor coupled between the sixth transistor and the second transistor.
Abstract:
A circuit and method for operating a switching mode power supply. A clock is driven by a current source to generate pulses at a fixed frequency using pulse width modulation for normal load demands. For light load demands, the current to the clock is reduced, and therefore the clock generates pulses at a lower, variable frequency and fixed duration using pulse frequency modulation. Thus, depending on the load condition, either fixed frequency pulses or fixed duration pulses are automatically provided to a power stage for conversion to an output voltage.
Abstract:
A device includes a first amplifier and a second amplifier. The first amplifier includes an inverting input configured to be coupled to a feedback node of an output of a power converter, a first non-inverting input configured to couple to a first voltage node, a second non-inverting input, and an output. The second amplifier includes an inverting input coupled to the output of the first amplifier, a non-inverting input coupled to a second voltage node, and an output. The device also includes a first transistor coupled to the output of the first amplifier and having a control terminal coupled to the output of the second amplifier, a capacitor coupled to a ground node and to the second non-inverting input of the first amplifier, and a current node coupled to the capacitor.
Abstract:
Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.
Abstract:
Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.
Abstract:
A system includes a current mirror coupled to a first transistor, the first transistor includes a first gate, a first current terminal, and a second current terminal, a controller coupled to the current mirror and a converter, the controller is to output a delayed signal for a second transistor, the second transistor being a part of the converter, and a source voltage coupled to the current mirror.
Abstract:
A device includes a first amplifier and a second amplifier. The first amplifier includes an inverting input configured to be coupled to a feedback node of an output of a power converter, a first non-inverting input configured to couple to a first voltage node, a second non-inverting input, and an output. The second amplifier includes an inverting input coupled to the output of the first amplifier, a non-inverting input coupled to a second voltage node, and an output. The device also includes a first transistor coupled to the output of the first amplifier and having a control terminal coupled to the output of the second amplifier, a capacitor coupled to a ground node and to the second non-inverting input of the first amplifier, and a current node coupled to the capacitor.
Abstract:
An example of an apparatus includes a bias circuit having first and second bias circuit outputs. The apparatus also includes a comparator having first and second comparator inputs. The apparatus also includes a first capacitor coupled between the second comparator input and the second bias circuit output. The apparatus also includes a first switch coupled between the second comparator input and the second bias circuit output. The apparatus also includes a second switch coupled between the first bias circuit output and an input terminal, a third switch coupled between the input terminal and the first comparator input, and a fourth switch coupled between the first bias circuit output and the first comparator input. The apparatus also includes a second capacitor coupled between the first comparator input and the second bias circuit output.
Abstract:
A system includes: an input voltage source; a power stage coupled to the input voltage source; a load coupled to an output of the power stage; and an error amplifier circuit coupled to the power stage. The error amplifier circuit includes an error amplifier; a transconductance stage coupled to an output of the error amplifier; an internal compensation switch; an external compensation switch; and control logic coupled to the internal compensation switch and the external compensation switch. The control logic is configured to selectively operate the internal compensation switch and the external compensation switch in one of an internal compensation mode and an external compensation mode.