Abstract:
A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.
Abstract:
A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.
Abstract:
A circuit includes a zero current detector (ZCD) circuit that senses an inductor current of an inductor and generates signal pulses indicating when an increasing cycle of the inductor current crosses a predetermined current value and when a decreasing cycle of the inductor current crosses the predetermined current value. A sync control provides a control signal specifying one of the signal pulses corresponding to the increasing or decreasing cycle of the inductor current. A sync selector circuit generates a sync pulse representing the signal pulse from the ZCD in response to the control signal. The sync pulse triggers a timing adjustment for a switch device.
Abstract:
A multiple-output integrated power factor correction system includes, for example, a processor that is formed in a substrate and is arranged to monitor each voltage output of two or more output stages of a power supply and in response to generate an individual voltage error signal for each monitored output stage. A combined output voltage error signal is generated in response to each of the individual voltage error signals. The voltage input to the power supply and the total inductor current of the power supply are monitored and used to generate a combined output voltage control signal in response to the monitored input voltage total inductor current as well as the combined output voltage error control signal. Each individual output voltage control signal for each monitored output stage is generated in response to each of the respective generated individual voltage error signals.
Abstract:
A device [200, para. 24] is configured to detect a zero voltage switching (ZVS) circuit [110, para. 14] output that includes a hard switching signal. The hard switching signal [114, para. 16] includes a false signal [116, para. 16] and a spike signal [118, para. 16]. Thereafter, the device generates digital pulse signals [312/314, para. 39] that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal [312, para. 41], and uses the digital pulse signal [314, para. 42] that corresponds to the spike signal for adjusting a timing [132, para. 20] of a pulse width modulation (PWM) switching cycle [Vgs 106, para. 32].
Abstract:
A multiple-output integrated power factor correction system includes, for example, a processor that is formed in a substrate and is arranged to monitor each voltage output of two or more output stages of a power supply and in response to generate an individual voltage error signal for each monitored output stage. A combined output voltage error signal is generated in response to each of the individual voltage error signals. The voltage input to the power supply and the total inductor current of the power supply are monitored and used to generate a combined output voltage control signal in response to the monitored input voltage total inductor current as well as the combined output voltage error control signal. Each individual output voltage control signal for each monitored output stage is generated in response to each of the respective generated individual voltage error signals.
Abstract:
A multiple-output integrated power factor correction system includes, for example, a processor that is formed in a substrate and is arranged to monitor each voltage output of two or more output stages of a power supply and in response to generate an individual voltage error signal for each monitored output stage. A combined output voltage error signal is generated in response to each of the individual voltage error signals. The voltage input to the power supply and the total inductor current of the power supply are monitored and used to generate a combined output voltage control signal in response to the monitored input voltage total inductor current as well as the combined output voltage error control signal. Each individual output voltage control signal for each monitored output stage is generated in response to each of the respective generated individual voltage error signals.
Abstract:
A circuit includes a zero current detector (ZCD) circuit that senses an inductor current of an inductor and generates signal pulses indicating when an increasing cycle of the inductor current crosses a predetermined current value and when a decreasing cycle of the inductor current crosses the predetermined current value. A sync control provides a control signal specifying one of the signal pulses corresponding to the increasing or decreasing cycle of the inductor current. A sync selector circuit generates a sync pulse representing the signal pulse from the ZCD in response to the control signal. The sync pulse triggers a timing adjustment for a switch device.
Abstract:
A digital power supply and power supply controller are presented, including a voltage control loop and a current control loop, with a controller for pulse width modulating a switching power supply according to a voltage control loop duty cycle output or a current control loop duty cycle output, in which the controller selectively presets the voltage control loop duty cycle output to a predetermined value before switching from current loop control to voltage loop control and/or inhibits increase in a voltage loop integrator value during current loop control to mitigate voltage overshoot.
Abstract:
A device [200] is configured to detect a zero voltage switching (ZVS) circuit [110] output that includes a hard switching signal. The hard switching signal [114] includes a false signal [116] and a spike signal [118]. Thereafter, the device generates digital pulse signals [312/314] that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal [312], and uses the digital pulse signal [314] that corresponds to the spike signal for adjusting a timing [132] of a pulse width modulation (PWM) switching cycle [Vgs ].