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公开(公告)号：US20190199240A1
公开(公告)日：2019-06-27
申请号：US16220724
申请日：2018-12-14
IPC分类号： H02M7/5395 , G01R19/175 , H02M1/08
CPC分类号： H02M7/5395 , G01R19/175 , H02M1/083 , H02M2001/0012 , H02M2001/0038
摘要： A device [200, para. 24] is configured to detect a zero voltage switching (ZVS) circuit [110, para. 14] output that includes a hard switching signal. The hard switching signal [114, para. 16] includes a false signal [116, para. 16] and a spike signal [118, para. 16]. Thereafter, the device generates digital pulse signals [312/314, para. 39] that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal [312, para. 41], and uses the digital pulse signal [314, para. 42] that corresponds to the spike signal for adjusting a timing [132, para. 20] of a pulse width modulation (PWM) switching cycle [Vgs 106, para. 32].
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公开(公告)号：US10944337B2
公开(公告)日：2021-03-09
申请号：US16220724
申请日：2018-12-14
IPC分类号： H02M7/5395 , H02M7/219 , H02M1/00
摘要： A device [200] is configured to detect a zero voltage switching (ZVS) circuit [110] output that includes a hard switching signal. The hard switching signal [114] includes a false signal [116] and a spike signal [118]. Thereafter, the device generates digital pulse signals [312/314] that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal [312], and uses the digital pulse signal [314] that corresponds to the spike signal for adjusting a timing [132] of a pulse width modulation (PWM) switching cycle [Vgs ].
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公开(公告)号：US10305385B2
公开(公告)日：2019-05-28
申请号：US15481181
申请日：2017-04-06
摘要： One example includes an interleaved resonant converter circuit. The circuit includes a plurality of resonant converter circuits that are each coupled to an output node and are configured to collectively generate an output voltage on the output node in response to a respective plurality of sets of switching signals at each of a respective plurality of phases. The circuit also includes a switching controller configured to generate each of the plurality of sets of switching signals having a variable duty-cycle relative to each other at each of the plurality of phases.
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公开(公告)号：US20190296648A1
公开(公告)日：2019-09-26
申请号：US16424248
申请日：2019-05-28
摘要： One example includes an interleaved resonant converter circuit. The circuit includes a plurality of resonant converter circuits that are each coupled to an output node and are configured to collectively generate an output voltage on the output node in response to a respective plurality of sets of switching signals at each of a respective plurality of phases. The circuit also includes a switching controller configured to generate each of the plurality of sets of switching signals having a variable duty-cycle relative to each other at each of the plurality of phases.
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5.发明授权Apparatus and method for a programmable timing in peak current mode controlled power converters 有权在峰值电流模式下的可编程定时控制功率转换器的装置和方法公开(公告)号：US08686767B1
公开(公告)日：2014-04-01
申请号：US13775154
申请日：2013-02-23
IPC分类号： G06F1/24
CPC分类号： H02M3/1588 , H02M1/38 , H02M3/157 , Y02B70/1466
摘要： An apparatus and a method for a programmable timing in digital integrated circuits implementing peak current mode controlled power converters are disclosed. The programmable dead-time is implemented by means implemented in hardware, software, and combination of hardware and software, carrying out setting a second timer value; setting a third timer value with respect to the second timer value; detecting a reset event; reloading a second counter from a current timer value to the second timer value upon detecting the reset event; resetting a second pulse width modulated waveform amplitude from a second amplitude value to a first amplitude value upon detecting the reset event; and setting a first pulse width modulated waveform from a first amplitude value to a second value upon the second counter reaching a third value.
摘要翻译： 公开了一种实现峰值电流模式控制功率转换器的数字集成电路中的可编程时序的装置和方法。 可编程死区时间由硬件，软件以及硬件与软件的组合实现，实现设定第二定时器值; 相对于第二定时器值设置第三定时器值; 检测复位事件; 在检测到复位事件时，将第二计数器从当前定时器值重新加载到第二定时器值; 在检测到复位事件时，将第二脉冲宽度调制波形振幅从第二幅度值复位到第一幅度值; 以及当所述第二计数器达到第三值时，将第一脉冲宽度调制波形从第一幅度值设置为第二值。
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公开(公告)号：US10530344B1
公开(公告)日：2020-01-07
申请号：US16399394
申请日：2019-04-30
IPC分类号： H03K3/017
摘要： In described examples, a method of generating a pulse width modulation (PWM) signal includes repeatedly master control counting, by a master control counter generator, which includes one or both of incrementing and decrementing a master control counter with a minimum value and a maximum value, and repeatedly slave control counting with a phase delay with respect to the master control counting, and during a transition period, slave control counting to a new maximum value or a new phase delay. A maximum count of the transition period is selected to result in the transition period reaching the minimum value at the new phase delay count. The PWM signal is generated by generating rising edges when the slave control counter reaches a rising edge threshold, and generating falling edges when the slave control counter reaches a falling edge threshold.
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7.发明申请APPARATUS AND METHOD FOR SELECTIVE AND ADAPTIVE SLOPE COMPENSATION IN PEAK CURRENT MODE CONTROLLED POWER CONVERTERS 有权峰值电流模式控制电源转换器中选择和自适应斜率补偿的装置和方法公开(公告)号：US20140239935A1
公开(公告)日：2014-08-28
申请号：US13775180
申请日：2013-02-23
IPC分类号： G05F3/02
CPC分类号： H02M3/1588 , H02M3/156 , H02M2001/0032 , H02M2001/385 , Y02B70/1466 , Y02B70/16
摘要： An apparatus and a method for selective and adaptive slope compensation in peak current mode controlled power converter are disclosed. The selective and adaptive slope compensation in peak current mode controlled power converter is implemented by hardware, software, and/or combination of both to carry out start of a pulse width modulated period and delay of a start of slope compensation by a first time from the starting of the pulse width modulated period.
摘要翻译： 公开了一种用于峰值电流模式控制功率转换器中的选择性和自适应斜率补偿的装置和方法。 峰值电流模式控制功率转换器中的选择和自适应斜率补偿由硬件，软件和/或两者的组合来实现，以便从第一次执行脉宽调制周期的开始和斜坡补偿开始延迟 开始脉宽调制周期。
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8.发明申请APPARATUS AND METHODS TO CONTROL PEAK CURRENT MODE CONTROLLED POWER CONVERTERS USING SELECTIVE NOISE BLANKING 有权使用选择性噪声净化控制峰值电流模式控制功率转换器的装置和方法公开(公告)号：US20140239922A1
公开(公告)日：2014-08-28
申请号：US13775182
申请日：2013-02-23
IPC分类号： G05F1/10
CPC分类号： G05F1/10 , H02M3/156 , H02M2001/0025 , H02M2001/0038
摘要： An apparatus and a method to control peak current mode controlled power converter system using selective noise blanking are disclosed. The control of the peak current mode controlled power converter system using selective noise blanking is implemented by hardware, software and/or combination of both to carry out adjusting a blanking time and a blanking time period to prevent change of an output of a pulse modulated waveform generator starting at the blanking time for the blanking time period.
摘要翻译： 公开了一种使用选择性噪声消隐来控制峰值电流模式受控功率转换器系统的装置和方法。 使用选择性噪声消隐的峰值电流模式控制功率转换器系统的控制由硬件，软件和/或两者的组合来实现，以执行调整消隐时间和消隐时间段，以防止脉冲调制波形的输出变化 发电机起始于消隐时间的消隐时间。
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公开(公告)号：US11916495B2
公开(公告)日：2024-02-27
申请号：US17194436
申请日：2021-03-08
IPC分类号： H02M7/219 , H02M7/5395 , H02M1/00
CPC分类号： H02M7/5395 , H02M7/219 , H02M1/0038 , H02M1/0058
摘要： A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.
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公开(公告)号：US20210194384A1
公开(公告)日：2021-06-24
申请号：US17194436
申请日：2021-03-08
IPC分类号： H02M7/5395 , H02M7/219
摘要： A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.
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