公开(公告)号：US20210320210A1

公开(公告)日：2021-10-14

申请号：US16847204

申请日：2020-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a semiconductor layer, a gate structure, source/drain regions, a bottom isolation layer, and a bottom spacer. The semiconductor layer is above the substrate. The gate structure is above the substrate and surrounds the semiconductor layer. The source/drain regions are on opposite sides of the semiconductor layer. The bottom isolation layer is between the substrate and the semiconductor layer. The bottom spacer is on a sidewall of the bottom isolation layer.

公开(公告)号：US20210119010A1

公开(公告)日：2021-04-22

申请号：US16656014

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi YEONG ,  Chien-Ning YAO ,  Chi-On CHUI

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first source/drain structure and a second source/drain structure in the substrate. The semiconductor device structure includes a gate stack over the substrate and between the first source/drain structure and the second source/drain structure. The gate stack includes a gate dielectric layer and a gate over the gate dielectric layer, a portion of the gate dielectric layer is adjacent to a first sidewall of the gate, the gate stack has a gap between the first sidewall and the portion of the gate dielectric layer, and the gap is a vacuum gap or an air gap.

公开(公告)号：US20240194758A1

公开(公告)日：2024-06-13

申请号：US18584862

申请日：2024-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang LIN ,  Kuan-Ting PAN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO ,  Kuo-Cheng CHIANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/78696

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

公开(公告)号：US20220246768A1

公开(公告)日：2022-08-04

申请号：US17723283

申请日：2022-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

Abstract: A device includes a substrate, a semiconductor layer, a gate structure, source/drain regions, a bottom isolation layer, and a bottom spacer. The semiconductor layer is above the substrate. The gate structure is above the substrate and surrounds the semiconductor layer. The source/drain regions are on opposite sides of the semiconductor layer. The bottom isolation layer is between the substrate and the semiconductor layer. The bottom spacer is on a sidewall of the bottom isolation layer. The bottom isolation layer has a seam therein, and the seam exposes a sidewall of the bottom spacer.

公开(公告)号：US20210391466A1

公开(公告)日：2021-12-16

申请号：US16899832

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi YEONG ,  Chi-On CHUI ,  Chien-Ning YAO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack wrapping around a top portion of the fin. The semiconductor device structure includes a first nanostructure over the fin and passing through the gate stack. The semiconductor device structure includes a second nanostructure over the first nanostructure and passing through the gate stack. The semiconductor device structure includes a stressor structure over the fin and connected to the first nanostructure and the second nanostructure. The semiconductor device structure includes a first inner spacer between the first portion and the stressor structure. The semiconductor device structure includes a second inner spacer between the second portion and the stressor structure.

公开(公告)号：US20250126837A1

公开(公告)日：2025-04-17

申请号：US18990878

申请日：2024-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Cheng CHEN ,  Zhi-Chang LIN ,  Jung-Hung CHANG ,  Chien-Ning YAO ,  Tsung-Han CHUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H10D30/67 ,  H01L21/762 ,  H10D30/01 ,  H10D84/83

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

公开(公告)号：US20230215950A1

公开(公告)日：2023-07-06

申请号：US18120879

申请日：2023-03-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78609 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.

公开(公告)号：US20230012216A1

公开(公告)日：2023-01-12

申请号：US17370833

申请日：2021-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang LIN ,  Kuan-Ting PAN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO ,  Kuo-Cheng CHIANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

公开(公告)号：US20220093785A1

公开(公告)日：2022-03-24

申请号：US17025903

申请日：2020-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Cheng CHEN ,  Zhi-Chang LIN ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Chien-Ning YAO ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234

Abstract: Embodiments of the present disclosure relate to an un-doped or low-doped epitaxial layer formed below the source/drain features. The un-doped or low-doped epitaxial layer protects the source/drain features from damage during replacement gate processes, and also prevent leakage currents in the mesa device. A semiconductor device is disclosed. The semiconductor device includes an epitaxial feature having a dopant of a first concentration, and a source/drain feature in contact with the epitaxial feature. The source/drain feature comprises the dopant of a second concentration, and the second concentration is higher than the first concentration.

公开(公告)号：US20220416036A1

公开(公告)日：2022-12-29

申请号：US17576748

申请日：2022-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Cheng CHEN ,  Zhi-Chang LIN ,  Jung-Hung CHANG ,  Chien-Ning YAO ,  Tsung-Han CHUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.