公开(公告)号：US11289602B2

公开(公告)日：2022-03-29

申请号：US16733398

申请日：2020-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chih-Sheng Chang ,  Tzu-Chiang Chen

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.

公开(公告)号：US11227828B2

公开(公告)日：2022-01-18

申请号：US16571214

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Chun-Chieh Lu ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L49/02

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a capacitor structure, and a conductive contact. The semiconductor substrate has at least one semiconductor fin thereon. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer and a first metal layer disposed on the ferroelectric layer. The capacitor structure is sandwiched between the conductive contact and the gate structure.

公开(公告)号：US20210210636A1

公开(公告)日：2021-07-08

申请号：US16733398

申请日：2020-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chih-Sheng Chang ,  Tzu-Chiang Chen

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.

公开(公告)号：US20210082801A1

公开(公告)日：2021-03-18

申请号：US16571214

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Chun-Chieh Lu ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a capacitor structure, and a conductive contact. The semiconductor substrate has at least one semiconductor fin thereon. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer and a first metal layer disposed on the ferroelectric layer. The capacitor structure is sandwiched between the conductive contact and the gate structure.

公开(公告)号：US10937783B2

公开(公告)日：2021-03-02

申请号：US15476221

申请日：2017-03-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wen Chang ,  Hong-Nien Lin ,  Chien-Hsing Lee ,  Chih-Sheng Chang ,  Ling-Yen Yeh ,  Wilman Tsai ,  Yee-Chia Yeo

IPC: H01L21/02 ,  H01L27/06 ,  H01L27/1159 ,  H01L29/417 ,  H01L27/088 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8234 ,  H01L49/02

Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

公开(公告)号：US10818562B2

公开(公告)日：2020-10-27

申请号：US16020860

申请日：2018-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Shiang Lin ,  Chia-Cheng Ho ,  Chun-Chieh Lu ,  Cheng-Yi Peng ,  Chih-Sheng Chang

IPC: H01L21/76 ,  H01L29/78 ,  H01L21/66 ,  G01R27/26

Abstract: A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric layer. The dielectric layer and the cap layer are annealed. The annealed cap layer is removed. A ferroelectricity of the annealed dielectric layer is in-line tested.

公开(公告)号：US10825899B2

公开(公告)日：2020-11-03

申请号：US16693058

申请日：2019-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Meng-Hsuan Hsiao ,  Tung-Ying Lee ,  Ling-Yen Yeh ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L27/108 ,  H01L27/12 ,  H01L27/11585 ,  H01L23/31 ,  H01L21/465 ,  H01L29/08 ,  H01L21/768 ,  H01L29/06 ,  H01L21/441 ,  H01L29/66 ,  H01L27/24 ,  H01L27/092 ,  H01L27/11592 ,  H01L29/778 ,  H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L21/3105 ,  H01L21/027

Abstract: A method of fabricating a semiconductor device includes forming a fin structure on a substrate, forming a channel layer on a sidewall and a top surface of the fin structure, and forming a gate stack over the channel layer. The channel layer includes a two-dimensional (2D) material. The gate stack includes a ferroelectric layer.

公开(公告)号：US10784362B2

公开(公告)日：2020-09-22

申请号：US15908348

申请日：2018-02-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh Lu ,  Carlos H. Diaz ,  Chih-Sheng Chang ,  Cheng-Yi Peng ,  Ling-Yen Yeh

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/324 ,  H01L21/02 ,  H01L49/02 ,  H01L29/66 ,  H01L21/28

Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.

公开(公告)号：US10732209B2

公开(公告)日：2020-08-04

申请号：US16588654

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chia-Cheng Ho ,  Ming-Shiang Lin ,  Chih-Sheng Chang ,  Carlos H. Diaz

IPC: G01R27/16 ,  H01L21/66

Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.

公开(公告)号：US10340366B2

公开(公告)日：2019-07-02

申请号：US15653094

申请日：2017-07-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chih Chieh Yeh ,  Chih-Sheng Chang ,  Hung-Li Chiang ,  Hung-Ming Chen ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.