公开(公告)号：US20240021476A1

公开(公告)日：2024-01-18

申请号：US18151181

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chun-Kai Chen

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L29/6656 ,  H01L21/76813 ,  H01L29/66545

Abstract: In an embodiment, a device includes: a source/drain region over a semiconductor substrate; a dielectric layer over the source/drain region, the dielectric layer including a first dielectric material; an inter-layer dielectric over the dielectric layer, the inter-layer dielectric including a second dielectric material and an impurity, the second dielectric material different from the first dielectric material, a first portion of the inter-layer dielectric having a first concentration of the impurity, a second portion of the inter-layer dielectric having a second concentration of the impurity, the first concentration less than the second concentration; and a source/drain contact extending through the inter-layer dielectric and the dielectric layer to contact the source/drain region, the first portion of the inter-layer dielectric disposed between the source/drain contact and the second portion of the inter-layer dielectric.

公开(公告)号：US20230050514A1

公开(公告)日：2023-02-16

申请号：US17399262

申请日：2021-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Kai Chen ,  Jei Ming Chen ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/311

Abstract: A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

公开(公告)号：US20240071815A1

公开(公告)日：2024-02-29

申请号：US18498851

申请日：2023-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Kai Chen ,  Jei Ming Chen ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76811 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877

Abstract: A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

公开(公告)号：US12183577B2

公开(公告)日：2024-12-31

申请号：US17332553

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Kai Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.

公开(公告)号：US11842922B2

公开(公告)日：2023-12-12

申请号：US17399262

申请日：2021-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Kai Chen ,  Jei Ming Chen ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76811 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877

Abstract: A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.

公开(公告)号：US20220102143A1

公开(公告)日：2022-03-31

申请号：US17332553

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Kai Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.

公开(公告)号：US20250079172A1

公开(公告)日：2025-03-06

申请号：US18953928

申请日：2024-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Kai Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.