中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.016 seconds)

    Fill structures with air gaps
    3.
    发明授权
    Fill structures with air gaps 有权

    公开(公告)号：US11961884B2

    公开(公告)日：2024-04-16

    申请号：US17549049

    申请日：2021-12-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsiu-Yung Lin ,  Yen Chuang ,  Min-Hao Hong

    IPC: H01L29/94 ,  H01L21/02 ,  H01L29/06 ,  H01L29/76 ,  H01L29/78

    CPC classification number: H01L29/0649 ,  H01L21/02252 ,  H01L29/7851

    Abstract: The present disclosure describes a semiconductor device with a fill structure. The semiconductor structure includes first and second fin structures on a substrate, an isolation region on the substrate and between the first and second fin structures, a first gate structure disposed on the first fin structure and the isolation region, a second gate structure disposed on the second fin structure and the isolation region, and the fill structure on the isolation region and between the first and second gate structures. The fill structure includes a dielectric structure between the first and second gate structures and an air gap enclosed by the dielectric structure. The air gap is below top surfaces of the first and second fin structures.

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10818790B2

    公开(公告)日：2020-10-27

    申请号：US16435070

    申请日：2019-06-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chih-Fen Chen ,  Chui-Ya Peng ,  Ching Yu ,  Pin-Hen Lin ,  Yen Chuang ,  Yuh-Ta Fan

    IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

    Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends substantially along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

    STACKED TRANSISTOR ISOLATION FEATURES AND METHODS OF FORMING THE SAME
    7.
    发明申请
    STACKED TRANSISTOR ISOLATION FEATURES AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20250048689A1

    公开(公告)日：2025-02-06

    申请号：US18364525

    申请日：2023-08-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ji-Yin Tsai ,  Zheng Hui Lim ,  Yen Chuang ,  Jet-Rung Chang ,  Ta-Chun Ma ,  Chii-Horng Li

    IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66

    Abstract: Methods of forming a stacked transistor are provided. One representative method may include patterning a first dummy nanostructure, a second dummy nanostructure, and a semiconductor nanostructure. The semiconductor nanostructure may be disposed between the first dummy nanostructure and the second dummy nanostructure. The first dummy nanostructure may comprise a first semiconductor material and the second dummy nanostructure may comprise a superlattice structure. The representative method may also include performing an etching process that simultaneously recesses the first dummy nanostructure to form a sidewall recess and removes the second dummy nanostructure to form an opening. The etching process selectively etches the superlattice structure at a faster rate than the first semiconductor material. The representative method may further include forming an inner spacer and an isolation structure in, respectively, the sidewall recess and the opening.

    Semiconductor device and manufacturing method thereof
    8.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11411108B2

    公开(公告)日：2022-08-09

    申请号：US17078856

    申请日：2020-10-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chih-Fen Chen ,  Chui-Ya Peng ,  Ching Yu ,  Pin-Hen Lin ,  Yen Chuang ,  Yuh-Ta Fan

    IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

    Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

Patent Agency Ranking