公开(公告)号：US20250048716A1

公开(公告)日：2025-02-06

申请号：US18365763

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen Chuang ,  Ji-Yin Tsai ,  Jet-Rung Chang ,  Zheng Hui Lim ,  Ta-Chun Ma

IPC: H01L21/8238 ,  H01L29/66

Abstract: Embodiments utilize a silicon germanium layer deposited to a low germanium percentage under a substrate. The substrate is used to form a field effect transistor FET structure. After formation of the FET, the silicon germanium layer is oxidized to drive germanium to a concentrated sublayer of the silicon germanium layer. The sublayer is used as a stop layer to remove the oxidized portion of the silicon germanium layer.

公开(公告)号：US20250089340A1

公开(公告)日：2025-03-13

申请号：US18408932

申请日：2024-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jet-Rung Chang ,  Ming-Hua Yu ,  Yi-Fang Pai

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device and the method of forming the same are provided. The semiconductor device may comprise a first plurality of nanostructures, a second plurality of nanostructures over a substrate, a first gate stack extending between the nanostructures of the first plurality of nanostructures, a second gate stack extending between the nanostructures of the second plurality of nanostructures, a first source/drain region in contact with a first nanostructure of the first plurality of nanostructures, a second source/drain region in contact with a first nanostructure of the second plurality of nanostructures, wherein the second source/drain region may be separated from the first source/drain region, a silicide layer between the first source/drain region and the second source/drain region, and an isolation layer between the silicide layer and the substrate.

公开(公告)号：US20250048689A1

公开(公告)日：2025-02-06

申请号：US18364525

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ji-Yin Tsai ,  Zheng Hui Lim ,  Yen Chuang ,  Jet-Rung Chang ,  Ta-Chun Ma ,  Chii-Horng Li

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66

Abstract: Methods of forming a stacked transistor are provided. One representative method may include patterning a first dummy nanostructure, a second dummy nanostructure, and a semiconductor nanostructure. The semiconductor nanostructure may be disposed between the first dummy nanostructure and the second dummy nanostructure. The first dummy nanostructure may comprise a first semiconductor material and the second dummy nanostructure may comprise a superlattice structure. The representative method may also include performing an etching process that simultaneously recesses the first dummy nanostructure to form a sidewall recess and removes the second dummy nanostructure to form an opening. The etching process selectively etches the superlattice structure at a faster rate than the first semiconductor material. The representative method may further include forming an inner spacer and an isolation structure in, respectively, the sidewall recess and the opening.

公开(公告)号：US10163669B2

公开(公告)日：2018-12-25

申请号：US15010935

申请日：2016-01-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ying-Chieh Hung ,  Ming-Hua Yu ,  Yi-Hung Lin ,  Jet-Rung Chang

IPC: G01B11/02 ,  H01L21/67 ,  G01B11/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/66

Abstract: A method for thickness measurement includes forming an implantation region in a semiconductor substrate. A semiconductor layer is formed on the implantation region of the semiconductor substrate. Modulated free carriers are generated in the implantation region of the semiconductor substrate. A probe beam is provided on the semiconductor layer and the implantation region of the semiconductor substrate with the modulated free carriers therein. The probe beam reflected from the semiconductor layer and the implantation region is detected to determine a thickness of the semiconductor layer.