公开(公告)号：US12302595B2

公开(公告)日：2025-05-13

申请号：US17648037

申请日：2022-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bor Chiuan Hsieh ,  Tsai-Jung Ho ,  Po-Cheng Shih ,  Tze-Liang Lee

IPC: H10D30/01 ,  H10D30/62 ,  H10D64/01

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming gate spacers on opposing sides of the dummy gate stack, forming a source/drain region on a side of the dummy gate stack, forming an inter-layer dielectric over the source/drain region, replacing the dummy gate stack with a replacement gate stack, recessing the replacement gate stack to form a recess between the gate spacers, depositing a liner extending into the recess, depositing a masking layer over the liner and extending into the recess, forming an etching mask covering a portion of the masking layer, and etching the inter-layer dielectric to form a source/drain contact opening. The source/drain region is underlying and exposed to the source/drain contact opening. A source/drain contact plug is formed in the source/drain contact opening. A gate contact plug extends between the gate spacers and electrically connecting to the replacement gate stack.

公开(公告)号：US12272554B2

公开(公告)日：2025-04-08

申请号：US18227231

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Lin Wei ,  Ming-Hui Weng ,  Chih-Cheng Liu ,  Yi-Chen Kuo ,  Yen-Yu Chen ,  Yahru Cheng ,  Jr-Hung Li ,  Ching-Yu Chang ,  Tze-Liang Lee ,  Chi-Ming Yang

IPC: H01L21/033 ,  G03F1/22 ,  G03F7/00 ,  H01L21/308

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers. The multilayer photoresist structure is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying developer to the selectively exposed multilayer photoresist structure to form the pattern.

公开(公告)号：US20250112102A1

公开(公告)日：2025-04-03

申请号：US18980281

申请日：2024-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Jen Sung ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/538 ,  H01L25/10

Abstract: A method includes bonding a first wafer to a second wafer, performing a trimming process on the first wafer, and depositing a sidewall protection layer contacting a sidewall of the first wafer. The depositing the sidewall protection layer includes depositing a high-density material in contact with the sidewall of the first wafer. The sidewall protection layer has a density higher than a density of silicon oxide. The method further includes removing a horizontal portion of the sidewall protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

公开(公告)号：US12237224B2

公开(公告)日：2025-02-25

申请号：US17710457

申请日：2022-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Jen Hung Wang ,  Tze-Liang Lee

IPC: H01L23/535 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.

公开(公告)号：US20240413215A1

公开(公告)日：2024-12-12

申请号：US18451986

申请日：2023-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen Lo ,  Syun-Ming Jang ,  Mu-Chieh Chang ,  Tze-Liang Lee

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A method includes forming a stack of layers, which includes a plurality of semiconductor nanostructures, and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, depositing a spacer layer extending into the lateral recesses, trimming the spacer layer to form inner spacers, and performing a treatment process to reduce dielectric constant values of the inner spacers.

公开(公告)号：US20240387701A1

公开(公告)日：2024-11-21

申请号：US18787308

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Jung Ho ,  Tze-Liang Lee

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a recess between gate spacers of the gate structure by recessing the gate structure below upper surfaces of the gate spacers; depositing a first layer of a dielectric material in the recess along sidewalls and a bottom of the recess; after depositing the first layer, performing a first etching process to remove portions of the first layer of the dielectric material; and after the first etching process, depositing a second layer of the dielectric material in the recess over the first layer of the dielectric material.

公开(公告)号：US20240387616A1

公开(公告)日：2024-11-21

申请号：US18781476

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Zhong Chen ,  JeiMing Chen ,  Tze-Liang Lee

IPC: H01G4/30

Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming an etch stop layer over the interconnect structure; and forming a first multi-layered structure over the etch stop layer, which includes: forming a first conductive layer over the etch stop layer; treating an upper layer of the first conductive layer with a plasma process; and forming a second conductive layer over the treated first conductive layer. The method further includes: patterning the first multi-layered structure to form a first electrode; forming a first dielectric layer over the first electrode; forming a second multi-layered structure over the first dielectric layer, the second multi-layered structure having the same layered structure as the first multi-layered structure; and patterning the second multi-layered structure to form a second electrode.

公开(公告)号：US20240387268A1

公开(公告)日：2024-11-21

申请号：US18789327

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Jen Hung Wang ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.

公开(公告)号：US20240384409A1

公开(公告)日：2024-11-21

申请号：US18788717

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Liang Lee ,  Po-Hsien Cheng

IPC: C23C16/455 ,  H01J37/32

Abstract: A deposition apparatus and a method are provided. A method includes placing a substrate over a platform in a chamber of a deposition system. A precursor material is introduced into the chamber. A first gas curtain is generated in front of a first electromagnetic (EM) radiation source coupled to the chamber. A plasma is generated from the precursor material in the chamber, wherein the plasma comprises dissociated components of the precursor material. The plasma is subjected to a first EM radiation from the first EM radiation source. The first EM radiation further dissociates the precursor material. A layer is deposited over the substrate. The layer includes a reaction product of the dissociated components of the precursor material.

公开(公告)号：US20240363713A1

公开(公告)日：2024-10-31

申请号：US18766767

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Jung Ho ,  Tze-Liang Lee

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78618

Abstract: A device includes a substrate including an active region, a gate stack over the active region, and a hard mask over the gate stack. The hard mask includes a capping layer, a buttress layer extending along sidewalls and a bottom of the capping layer, and a liner layer extending along sidewalls and a bottom of the buttress layer. The buttress layer includes a metal oxide material or a metal nitride material.