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    EVALUATION OBJECT PATTERN DETERMINING APPARATUS, EVALUATION OBJECT PATTERN DETERMINING METHOD, EVALUATION OBJECT PATTERN DETERMINING PROGRAM AND PATTERN EVALUATING SYSTEM
    1.
    发明申请
    EVALUATION OBJECT PATTERN DETERMINING APPARATUS, EVALUATION OBJECT PATTERN DETERMINING METHOD, EVALUATION OBJECT PATTERN DETERMINING PROGRAM AND PATTERN EVALUATING SYSTEM 失效
    评估对象模式确定设备，评估对象模式确定方法，评估对象模式确定程序和模式评估系统

    公开(公告)号：US20090110262A1

    公开(公告)日：2009-04-30

    申请号：US12257551

    申请日：2008-10-24

    申请人： Takashi Noguchi ,  Shigetoshi Sameshima ,  Shigeki Kurihara ,  Tamao Ishikawa ,  Yutaka Tandai

    发明人： Takashi Noguchi ,  Shigetoshi Sameshima ,  Shigeki Kurihara ,  Tamao Ishikawa ,  Yutaka Tandai

    IPC分类号： G06K9/00

    CPC分类号： G06K9/00 ,  G06K2209/19 ,  G06T7/0004

    摘要： There is provided an evaluation object pattern determining apparatus capable of determining local patterns to be evaluated. The apparatus is for use in a pattern evaluating system storing patterns of a LSI chip as CAD data, picking out coordinates of local patterns whose process margin is small from the CAD data by way of simulation and assisting observation of the local patterns produced in a fabrication line. The apparatus includes a risk level map creating section for creating risk level maps in which risk areas are disposed. The risk area is assigned with a risk level obtained by digitizing that the risk area is an area whose process margin is smaller than other areas. The apparatus also includes a superimposition processing section for superimposing the coordinates of the local patterns with the risk level map to pick out the coordinates of the local patterns located within the risk area.

    摘要翻译： 提供了一种能够确定要评估的局部图案的评估对象图案确定装置。 该装置用于将LSI芯片的图案作为CAD数据存储的图案评估系统中，通过模拟从CAD数据中选出处理余量小的局部图案的坐标，并辅助观察在制造中产生的局部图案 线。 该装置包括用于创建其中设置风险区域的风险等级图的风险等级图创建部分。 风险区域被分配为通过数字化风险区域是其过程边缘小于其他区域的区域获得的风险水平。 该装置还包括叠加处理部分，用于将本地模式的坐标与风险等级图叠加，以选出位于风险区域内的局部模式的坐标。

    Evaluation object pattern determining apparatus, evaluation object pattern determining method, evaluation object pattern determining program and pattern evaluating system
    2.
    发明授权
    Evaluation object pattern determining apparatus, evaluation object pattern determining method, evaluation object pattern determining program and pattern evaluating system 失效
    评估对象图案确定装置，评价对象图案确定方法，评价对象图案确定程序和图案评价系统

    公开(公告)号：US08139845B2

    公开(公告)日：2012-03-20

    申请号：US12257551

    申请日：2008-10-24

    申请人： Takashi Noguchi ,  Shigetoshi Sameshima ,  Shigeki Kurihara ,  Tamao Ishikawa ,  Yutaka Tandai

    发明人： Takashi Noguchi ,  Shigetoshi Sameshima ,  Shigeki Kurihara ,  Tamao Ishikawa ,  Yutaka Tandai

    IPC分类号： G06K9/62

    CPC分类号： G06K9/00 ,  G06K2209/19 ,  G06T7/0004

    摘要： There is provided an evaluation object pattern determining apparatus capable of determining local patterns to be evaluated. The apparatus is for use in a pattern evaluating system storing patterns of a LSI chip as CAD data, picking out coordinates of local patterns whose process margin is small from the CAD data by way of simulation and assisting observation of the local patterns produced in a fabrication line. The apparatus includes a risk level map creating section for creating risk level maps in which risk areas are disposed. The risk area is assigned with a risk level obtained by digitizing that the risk area is an area whose process margin is smaller than other areas. The apparatus also includes a superimposition processing section for superimposing the coordinates of the local patterns with the risk level map to pick out the coordinates of the local patterns located within the risk area.

    摘要翻译： 提供了一种能够确定要评估的局部图案的评估对象图案确定装置。 该装置用于将LSI芯片的图案作为CAD数据存储的图案评估系统中，通过模拟从CAD数据中选出处理余量小的局部图案的坐标，并辅助观察在制造中产生的局部图案 线。 该装置包括用于创建其中设置风险区域的风险等级图的风险等级图创建部分。 风险区域被分配为通过数字化风险区域是其过程边缘小于其他区域的区域获得的风险水平。 该装置还包括叠加处理部分，用于将本地模式的坐标与风险等级图叠加以选出位于风险区域内的局部模式的坐标。

    SEMICONDUCTOR DEFECT INTEGRATED PROJECTION METHOD AND DEFECT INSPECTION SUPPORT APPARATUS EQUIPPED WITH SEMICONDUCTOR DEFECT INTEGRATED PROJECTION FUNCTION
    3.
    发明申请
    SEMICONDUCTOR DEFECT INTEGRATED PROJECTION METHOD AND DEFECT INSPECTION SUPPORT APPARATUS EQUIPPED WITH SEMICONDUCTOR DEFECT INTEGRATED PROJECTION FUNCTION 审中-公开
    半导体缺陷综合投影方法和缺陷检查支持装置配备半导体缺陷综合投影函数

    公开(公告)号：US20110296362A1

    公开(公告)日：2011-12-01

    申请号：US13147899

    申请日：2010-02-01

    申请人： Tamao Ishikawa ,  Yutaka Tandai ,  Shigeki Kurihara

    发明人： Tamao Ishikawa ,  Yutaka Tandai ,  Shigeki Kurihara

    IPC分类号： G06F17/50

    CPC分类号： G06T7/001 ,  G06F17/5068 ,  G06T2207/30148 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention comprises: a design layout data read part that acquires design layout data including location information of design circuit patterns used in steps of semiconductor fabrication; a wafer-chip information read part that acquires, from among data concerning a wafer on which a plurality of the design circuit patterns are formed per chip, wafer-chip information including at least design cell location information; a defect data read part that acquires defect data including location information of defects that occurred in the steps; a design layout data tracing processing part that creates a design layout data defect integrated projection display view by performing, based on the design layout data and the wafer-chip information, an integrated projection process on, among the design layout data, design layout data for a step in which a defect occurred and the defect data; and a defect integrated projection display apparatus that displays the design layout data defect integrated projection display view.

    摘要翻译： 本发明包括：设计布局数据读取部分，其获取包括在半导体制造步骤中使用的设计电路图案的位置信息的设计布局数据; 晶片芯片信息读取部，其从关于其上形成有多个设计电路图案的晶片的数据的数据中获取至少包括设计单元位置信息的晶片芯片信息; 缺陷数据读取部，其获取包括在步骤中发生的缺陷的位置信息的缺陷数据; 设计布局数据跟踪处理部，其通过基于设计布局数据和晶片芯片信息，通过在设计布局数据之间进行设计布局数据的设计布局数据，从而生成设计布局数据缺陷集成投影显示视图 发生缺陷的步骤和缺陷数据; 以及显示设计布局数据缺陷集成投影显示视图的缺陷集成投影显示装置。

    Sound source device
    6.
    发明授权
    Sound source device 有权
    声源设备

    公开(公告)号：US06506968B1

    公开(公告)日：2003-01-14

    申请号：US09701151

    申请日：2001-03-21

    申请人： Shigeki Kurihara

    发明人： Shigeki Kurihara

    IPC分类号： G10H700

    CPC分类号： G10H7/02 ,  G10H5/10 ,  G10H7/00 ,  G10H7/10 ,  G10H2250/235

    摘要： The present invention relates to a sound source device, and more particularly, it aims at providing a sound source device, in which a sufficient sound emitting quantity can be attained, capable of obtaining a reproduced sound of musically rich expression. And, in order to attain the aforementioned object, it is possible to solve such a problem that energy density is low and sound emitting efficiency is inferior by employing a pseudo-rectangular wave increasing spectral density as waveform data input in a waveform table (TB). For this, it is rendered a spectrum including spectral lines X1, X2, X3 and X4 in a range matching with a frequency domain (HR) having high sound emitting efficiency and including even harmonics.

    摘要翻译： 声源装置技术领域本发明涉及一种声源装置，更具体地说，本发明的目的在于提供一种能够获得足够的声音发射量的声源装置，能够获得音乐丰富的表达的再现声音。为了 达成上述目的，通过采用增加频谱密度的伪矩形波作为在波形表（TB）中输入的波形数据，可以解决能量密度低和发声效率差的问题。 为此，在与具有高发音效率并且包括均匀谐波的频域（HR）匹配的范围内，将谱线X1，X2，X3和X4的频谱渲染。