公开(公告)号：US08675949B2

公开(公告)日：2014-03-18

申请号：US13266800

申请日：2010-03-25

申请人： Yuji Takagi ,  Minoru Harada ,  Yuichi Hamamura

发明人： Yuji Takagi ,  Minoru Harada ,  Yuichi Hamamura

IPC分类号： G06K9/00

CPC分类号： G01N21/9501 ,  G01N21/956 ,  G01N2021/8867 ,  H01L22/12 ,  H01L22/20

摘要： The present invention relates to semiconductor inspection and provides a technology capable of efficiently detecting a systematic defect. In the present system, with regard to the process (S7, S8) of matching hot spot (HS) points that can be simulated in advance and defect points obtained as a result of a visual inspection each other and the unmatched defect points, a process (S6, S9) of classifying the defect points into groups based on similarity of pattern layout at the defect points to determine the defects belonging to a pattern layout where defects frequently occur, thereby reliably detecting the systematic defect. Also, with a process (S11) of acquiring an uneven distribution in a defect occurrence distribution on a wafer, the systematic defect occurring due to topography of the wafer can also be detected.

摘要翻译： 本发明涉及半导体检查，并且提供能够有效地检测系统缺陷的技术。 在本系统中，关于可以预先模拟的热点（HS）点和作为目视检查的结果获得的缺陷点与不匹配的缺陷点的处理（S7，S8），处理 （S6，S9），根据缺陷点的图案布局的相似度将缺陷点分类成组，以确定属于频繁发生缺陷的图案布局的缺陷，从而可靠地检测系统缺陷。 此外，通过获取晶片上的缺陷发生分布中的不均匀分布的处理（S11），也可以检测由于晶片的形貌而发生的系统缺陷。

公开(公告)号：US07062081B2

公开(公告)日：2006-06-13

申请号：US09783604

申请日：2001-02-15

申请人： Atsushi Shimoda ,  Ichirou Ishimaru ,  Yuji Takagi ,  Takuo Tamura ,  Yuichi Hamamura ,  Kenji Watanabe ,  Yasuhiko Ozawa ,  Seiji Isogai

发明人： Atsushi Shimoda ,  Ichirou Ishimaru ,  Yuji Takagi ,  Takuo Tamura ,  Yuichi Hamamura ,  Kenji Watanabe ,  Yasuhiko Ozawa ,  Seiji Isogai

IPC分类号： G06K9/00

CPC分类号： G06T7/0004 ,  G06T2207/30148 ,  H01L22/20

摘要： In order to allow critical flaws in an inspected item to be determined early during a production process, the present invention includes the following steps: a step of detecting defects in a production process for the inspected item and storing defect positions; a step of collecting detailed defect information and storing the detailed information in association with defect positions; a step of storing positions at which flaws were generated based on a final inspection of the inspected item; a step of comparing defect positions with positions at which flaws were generated; and a step of classifying and displaying detailed information based on the comparison results.

摘要翻译： 为了在生产过程中早期确定检查项目中的关键缺陷，本发明包括以下步骤：检测检查项目的生产过程中的缺陷并存储缺陷位置的步骤; 收集详细缺陷信息并存储与缺陷位置相关联的详细信息的步骤; 基于检查项目的最终检查来存储产生缺陷的位置的步骤; 将缺陷位置与产生缺陷的位置进行比较的步骤; 并根据比较结果对详细信息进行分类和显示。

公开(公告)号：US06841405B2

公开(公告)日：2005-01-11

申请号：US10269268

申请日：2002-10-10

申请人： Yuichi Hamamura ,  Takaaki Kumazawa ,  Hisao Asakura ,  Aritoshi Sugimoto ,  Kazuyuki Tsunokuni

发明人： Yuichi Hamamura ,  Takaaki Kumazawa ,  Hisao Asakura ,  Aritoshi Sugimoto ,  Kazuyuki Tsunokuni

IPC分类号： G01R31/28 ,  H01L21/00

CPC分类号： G01R31/2812 ,  G01R31/2818

摘要： A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.

摘要翻译： 电子设备的制造方法是使用测试结构提高测试效率并提高产量。 该制造方法使用设置在形成于基板上的绝缘层上的第一引线和与基板电连接并设置在绝缘层上的第二引线进行测试，并基于制造试验的结果来管理电子设备 电子设备。 该制造方法包括通过测量第一引线的两端之间的电阻和通过测量第一和第二引线是否短路的步骤来测试第一引线是否断开的步骤 第一引线与基板之间的电阻。

公开(公告)号：US06344115B1

公开(公告)日：2002-02-05

申请号：US09417996

申请日：1999-10-13

申请人： Junzou Azuma ,  Akira Shimase ,  Yuichi Hamamura ,  Hidemi Koike

发明人： Junzou Azuma ,  Akira Shimase ,  Yuichi Hamamura ,  Hidemi Koike

IPC分类号： C23C1400

CPC分类号： H01J37/18 ,  C23C16/26 ,  H01J2237/317

摘要： A pattern forming method using an improved charged particle beam process, and a charged particle beam processing system prevent effectively the corrosion of a workpiece by a reactive gas adsorbed by and adhering to the surface of the workpiece when the workpiece is taken out into the atmosphere after pattern formation. The charged particle beam processing system comprises, as principal components, an ion beam chamber provided with an ion beam optical system, a processing chamber provided with a gas nozzle through which a reactive gas is blown against a workpiece, a load-lock chamber connected through a gate valve to the processing chamber. The load-lock chamber is capable of producing a plasma of an inert gas for processing the surface of the workpiece by sputtering. The workpiece is returned to the load-lock chamber after a pattern has been formed thereon in the processing chamber by reactive processing including irradiating the surface of the workpiece with a charged particle beam in an environment of the reactive gas, and the workpiece is subjected to a plasma process to remove the reactive gas adsorbed by the workpiece during pattern formation and adhering to the workpiece.

摘要翻译： 使用改进的带电粒子束工艺的图案形成方法和带电粒子束处理系统，当工件被排出到大气中之后，通过被吸收并附着在工件表面上的反应气体有效地防止工件的腐蚀 图案形成。 带电粒子束处理系统作为主要部件包括设置有离子束光学系统的离子束室，设置有气体喷嘴的处理室，反应气体通过该喷嘴吹向工件，负载锁定室通过 一个闸阀到处理室。 负载锁定室能够产生用于通过溅射处理工件的表面的惰性气体的等离子体。 在通过反应性处理在处理室中形成图案之后，工件返回到装载锁定室，包括在反应气体的环境中用带电粒子束照射工件的表面，并且对工件进行 等离子体处理，以在图案形成期间去除被工件吸附的反应气体并附着到工件上。

公开(公告)号：US08995748B2

公开(公告)日：2015-03-31

申请号：US13375880

申请日：2010-06-01

申请人： Tsunehiro Sakai ,  Shigeki Kurihara ,  Yutaka Tandai ,  Tamao Ishikawa ,  Yuichi Hamamura ,  Tomohiro Funakoshi ,  Seiji Isogai ,  Katsuhiko Ichinose

发明人： Tsunehiro Sakai ,  Shigeki Kurihara ,  Yutaka Tandai ,  Tamao Ishikawa ,  Yuichi Hamamura ,  Tomohiro Funakoshi ,  Seiji Isogai ,  Katsuhiko Ichinose

IPC分类号： G06T7/00 ,  G01N21/95 ,  H01L21/66

CPC分类号： G06T7/001 ,  G01N21/9501 ,  G06T7/30 ,  G06T2200/24 ,  G06T2207/10056 ,  G06T2207/30148 ,  H01L22/12 ,  H01L22/20

摘要： A defect image processing apparatus uses a normalized cross correlation to image-match a layout image (52) acquired from a design data with an image acquired by removing, from a defect image (53), the defect area portions thereof, and displays, as a result of that matching, a layout image and defect image (54) on the display device. In the displayed layout image & defect image (54), not only the layout image, the layer of which is the same as that of the defect image (53), but also a layout image of another layer is displayed superimposed on the defect image (53). This makes it easier to analyze the factor of a systematic defect having occurred due to a positional relationship with another layer.

摘要翻译： 缺陷图像处理装置使用归一化互相关，将从设计数据获取的布局图像（52）图像匹配到通过从缺陷图像（53）中删除其缺陷区域部分而获取的图像，并将其显示为 该匹配的结果，布局图像和缺陷图像（54）在显示装置上。 在显示的布局图像和缺陷图像（54）中，不仅叠加在缺陷图像上显示其图层与缺陷图像（53）相同的布局图像，而且还显示另一层的布局图像 （53）。 这使得更容易分析由于与另一层的位置关系而发生的系统缺陷的因素。

公开(公告)号：US08612811B2

公开(公告)日：2013-12-17

申请号：US13119633

申请日：2009-09-04

申请人： Chizu Matsumoto ,  Yuichi Hamamura ,  Yoshiyuki Tsunoda ,  Kazuyuki Tsunokuni

发明人： Chizu Matsumoto ,  Yuichi Hamamura ,  Yoshiyuki Tsunoda ,  Kazuyuki Tsunokuni

IPC分类号： G11C29/56

CPC分类号： G11C29/006 ,  G06F17/5018 ,  G06F2217/10 ,  G11C29/54 ,  G11C29/56004

摘要： In a managing system for a semiconductor manufacturing apparatus, a predicting unit 121 predicts a characteristic defective ratio and a foreign-substance defective ratio of each process obtains an actual defective ratio of each fail bit mode and a critical area of each process and each fail bit mode, calculates the number of foreign substances of each process by using the actual defective ratio of each fail bit mode and the critical area of each process and each fail bit mode, the fail bit mode being except for an arbitrary fail bit mode, calculates a foreign-substance defective ratio of each process and a foreign-substance defective ratio of each fail bit mode by using the number of foreign substances, and calculates a characteristic defective ratio of the arbitrary fail bit mode based on the foreign-substance defective ratio and actual defective ratio of each fail bit mode.

摘要翻译： 在半导体制造装置的管理系统中，预测单元121预测每个处理的特征缺陷率和异物缺陷率，获得每个故障位模式和每个处理的临界区域的实际缺陷率以及每个故障位 模式，通过使用每个故障位模式的实际故障率和每个过程的关键区域以及每个故障位模式来计算每个过程的异物数量，故障位模式除了任意故障位模式，计算出 通过使用异物数量，每个处理的异物缺陷率和每个故障位模式的异物缺陷率，并且基于异物缺陷率和实际值计算任意故障位模式的特征缺陷率 每个故障位模式的故障率。

公开(公告)号：US20120141011A1

公开(公告)日：2012-06-07

申请号：US13375880

申请日：2010-06-01

申请人： Tsunehiro Sakai ,  Shigeki Kurihara ,  Yutaka Tandai ,  Tamao Ishikawa ,  Yuichi Hamamura ,  Tomohiro Funakoshi ,  Seiji Isogai ,  Katsuhiko Ichinose

发明人： Tsunehiro Sakai ,  Shigeki Kurihara ,  Yutaka Tandai ,  Tamao Ishikawa ,  Yuichi Hamamura ,  Tomohiro Funakoshi ,  Seiji Isogai ,  Katsuhiko Ichinose

IPC分类号： G06K9/00

CPC分类号： G06T7/001 ,  G01N21/9501 ,  G06T7/30 ,  G06T2200/24 ,  G06T2207/10056 ,  G06T2207/30148 ,  H01L22/12 ,  H01L22/20

摘要： A defect image processing apparatus uses a normalized cross correlation to image-match a layout image (52) acquired from a design data with an image acquired by removing, from a defect image (53), the defect area portions thereof, and displays, as a result of that matching, a layout image and defect image (54) on the display device. In the displayed layout image & defect image (54), not only the layout image, the layer of which is the same as that of the defect image (53), but also a layout image of another layer is displayed superimposed on the defect image (53). This makes it easier to analyze the factor of a systematic defect having occurred due to a positional relationship with another layer.

摘要翻译： 缺陷图像处理装置使用归一化互相关，将从设计数据获取的布局图像（52）图像匹配到通过从缺陷图像（53）中删除其缺陷区域部分而获取的图像，并将其显示为 该匹配的结果，布局图像和缺陷图像（54）在显示装置上。 在显示的布局图像和缺陷图像（54）中，不仅叠加在缺陷图像上显示其图层与缺陷图像（53）相同的布局图像，而且还显示另一层的布局图像 （53）。 这使得更容易分析由于与另一层的位置关系而发生的系统缺陷的因素。

公开(公告)号：US07301146B2

公开(公告)日：2007-11-27

申请号：US11201222

申请日：2005-08-11

申请人： Satoshi Tomimatsu ,  Hidemi Koike ,  Junzo Azuma ,  Tohru Ishitani ,  Aritoshi Sugimoto ,  Yuichi Hamamura ,  Isamu Sekihara ,  Akira Shimase

发明人： Satoshi Tomimatsu ,  Hidemi Koike ,  Junzo Azuma ,  Tohru Ishitani ,  Aritoshi Sugimoto ,  Yuichi Hamamura ,  Isamu Sekihara ,  Akira Shimase

IPC分类号： G01N23/00 ,  G21K7/00

CPC分类号： G01Q10/06 ,  G01N23/04 ,  G01N23/225 ,  G01R31/2886 ,  G01R31/311 ,  H01J37/28

摘要： A probe driving method and a probe apparatus for bringing a probe into contact with the surface of a sample in a safe and efficient manner by monitoring the probe height. Information about the height of the probe from the sample surface is obtained by detecting a probe shadow (54) appearing immediately before the probe contacts the sample, or based on a change in relative positions of a probe image and a sample image that are formed as an ion beam is irradiated diagonally.

摘要翻译： 探针驱动方法和探针装置，用于通过监测探针高度，以安全和有效的方式使探针与样品的表面接触。 通过检测在探针接触样品之前出现的探针阴影（54），或者基于探针图像和样品图像的相对位置的变化，获得关于来自样品表面的探针的高度的信息， 对角线照射离子束。

公开(公告)号：US06770496B2

公开(公告)日：2004-08-03

申请号：US10269411

申请日：2002-10-10

申请人： Yuichi Hamamura ,  Takaaki Kumazawa ,  Hisao Asakura ,  Aritoshi Sugimoto ,  Kazuyuki Tsunokuni

发明人： Yuichi Hamamura ,  Takaaki Kumazawa ,  Hisao Asakura ,  Aritoshi Sugimoto ,  Kazuyuki Tsunokuni

IPC分类号： H01L2166

CPC分类号： G01R31/2812 ,  G01R31/2818

摘要： A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.

摘要翻译： 电子设备的制造方法是使用测试结构提高测试效率并提高产量。 该制造方法使用设置在形成于基板上的绝缘层上的第一引线和与基板电连接并设置在绝缘层上的第二引线进行测试，并基于制造试验的结果来管理电子设备 电子设备。 该制造方法包括通过测量第一引线的两端之间的电阻和通过测量第一和第二引线是否短路的步骤来测试第一引线是否断开的步骤 第一引线与基板之间的电阻。

公开(公告)号：US20140177940A1

公开(公告)日：2014-06-26

申请号：US14236887

申请日：2011-05-28

申请人： Ryo Nakagaki ,  Yuichi Hamamura ,  Yuji Enomoto ,  Yutaka Tandai ,  Tsunehiro Sakai ,  Kazuhisa Hasumi

发明人： Ryo Nakagaki ,  Yuichi Hamamura ,  Yuji Enomoto ,  Yutaka Tandai ,  Tsunehiro Sakai ,  Kazuhisa Hasumi

IPC分类号： G06T7/00 ,  G06F17/50

CPC分类号： G06T7/0006 ,  G06F17/5081 ,  G06T2207/10061 ,  G06T2207/30148 ,  H01L22/12

摘要： A desired area is extracted by directly analyzing information recorded in a design layout, an inspection recipe is generated by using this extraction method, and an efficient inspection is realized. The invention makes it easy to extract an area of a desired circuit module such as a memory mat by analyzing hierarchy information of design layout data, calculating reference frequency of each one cell in the design layout data that is its internal data, sorting the cells in order of increasing reference frequency, searching the object, and tracing its upper cell.

摘要翻译： 通过直接分析设计布局中记录的信息来提取期望的区域，通过使用该提取方法生成检查配方，并且实现有效的检查。 本发明通过分析设计布局数据的层次信息，计算作为其内部数据的设计布局数据中的每一个单元的参考频率，对存储器垫等期望的电路模块的区域进行抽取， 增加参考频率，搜索对象和跟踪其上位单元的顺序。