公开(公告)号：US20090110262A1

公开(公告)日：2009-04-30

申请号：US12257551

申请日：2008-10-24

申请人： Takashi Noguchi ,  Shigetoshi Sameshima ,  Shigeki Kurihara ,  Tamao Ishikawa ,  Yutaka Tandai

发明人： Takashi Noguchi ,  Shigetoshi Sameshima ,  Shigeki Kurihara ,  Tamao Ishikawa ,  Yutaka Tandai

IPC分类号： G06K9/00

CPC分类号： G06K9/00 ,  G06K2209/19 ,  G06T7/0004

摘要： There is provided an evaluation object pattern determining apparatus capable of determining local patterns to be evaluated. The apparatus is for use in a pattern evaluating system storing patterns of a LSI chip as CAD data, picking out coordinates of local patterns whose process margin is small from the CAD data by way of simulation and assisting observation of the local patterns produced in a fabrication line. The apparatus includes a risk level map creating section for creating risk level maps in which risk areas are disposed. The risk area is assigned with a risk level obtained by digitizing that the risk area is an area whose process margin is smaller than other areas. The apparatus also includes a superimposition processing section for superimposing the coordinates of the local patterns with the risk level map to pick out the coordinates of the local patterns located within the risk area.

摘要翻译： 提供了一种能够确定要评估的局部图案的评估对象图案确定装置。 该装置用于将LSI芯片的图案作为CAD数据存储的图案评估系统中，通过模拟从CAD数据中选出处理余量小的局部图案的坐标，并辅助观察在制造中产生的局部图案 线。 该装置包括用于创建其中设置风险区域的风险等级图的风险等级图创建部分。 风险区域被分配为通过数字化风险区域是其过程边缘小于其他区域的区域获得的风险水平。 该装置还包括叠加处理部分，用于将本地模式的坐标与风险等级图叠加，以选出位于风险区域内的局部模式的坐标。

公开(公告)号：US08139845B2

公开(公告)日：2012-03-20

申请号：US12257551

申请日：2008-10-24

申请人： Takashi Noguchi ,  Shigetoshi Sameshima ,  Shigeki Kurihara ,  Tamao Ishikawa ,  Yutaka Tandai

发明人： Takashi Noguchi ,  Shigetoshi Sameshima ,  Shigeki Kurihara ,  Tamao Ishikawa ,  Yutaka Tandai

IPC分类号： G06K9/62

CPC分类号： G06K9/00 ,  G06K2209/19 ,  G06T7/0004

摘要： There is provided an evaluation object pattern determining apparatus capable of determining local patterns to be evaluated. The apparatus is for use in a pattern evaluating system storing patterns of a LSI chip as CAD data, picking out coordinates of local patterns whose process margin is small from the CAD data by way of simulation and assisting observation of the local patterns produced in a fabrication line. The apparatus includes a risk level map creating section for creating risk level maps in which risk areas are disposed. The risk area is assigned with a risk level obtained by digitizing that the risk area is an area whose process margin is smaller than other areas. The apparatus also includes a superimposition processing section for superimposing the coordinates of the local patterns with the risk level map to pick out the coordinates of the local patterns located within the risk area.

摘要翻译： 提供了一种能够确定要评估的局部图案的评估对象图案确定装置。 该装置用于将LSI芯片的图案作为CAD数据存储的图案评估系统中，通过模拟从CAD数据中选出处理余量小的局部图案的坐标，并辅助观察在制造中产生的局部图案 线。 该装置包括用于创建其中设置风险区域的风险等级图的风险等级图创建部分。 风险区域被分配为通过数字化风险区域是其过程边缘小于其他区域的区域获得的风险水平。 该装置还包括叠加处理部分，用于将本地模式的坐标与风险等级图叠加以选出位于风险区域内的局部模式的坐标。

公开(公告)号：US09377478B2

公开(公告)日：2016-06-28

申请号：US13322773

申请日：2010-04-28

申请人： Takashi Noguchi ,  Yoshiyuki Tajima ,  Koji Kamoshida ,  Naomi Ishii

发明人： Takashi Noguchi ,  Yoshiyuki Tajima ,  Koji Kamoshida ,  Naomi Ishii

IPC分类号： G06F15/173 ,  G01N35/02 ,  G01N35/00

CPC分类号： G01N35/02 ,  G01N35/00 ,  G01N35/00732 ,  G01N35/0092 ,  G01N35/0095

摘要： There is provided a sample test system which can execute a prior process for a specific sample in consideration of priorities and process progresses of a plurality of samples processed in the sample test system. The sample test system includes a sample-test-device management server 101, when a specific-sample prior process request containing a specific sample ID and a prior-process-request level identification code is accepted from a sample access system 108, which selects a specific-sample prior-process-policy determination table based on the prior-process-request level identification code attached to the specific-sample prior process request, which determines a specific-sample prior process policy based on the specific-sample prior-process-policy determination table and a process state of the sample, which specifies a sample ID regarding the specific sample ID, and which transmits the specific-sample prior process policy to a sample-test-device group 119.

摘要翻译： 提供了一种样本测试系统，其可以考虑到在样本测试系统中处理的多个样本的优先级和处理进程，对特定样本执行先前的过程。 样本测试系统包括样本测试设备管理服务器101，当从样本访问系统108接收到包含特定样本ID和先前处理请求级别识别码的特定样本先验处理请求时，该样本测试设备管理服务器101选择 基于与特定样本先验过程请求相关联的先前过程请求级别标识代码的特定样本先前过程策略确定表，其基于特定样本先前处理过程策略确定特定样本先验过程策略， 策略确定表和样本的处理状态，其指定关于特定样本ID的样本ID，并将特定样本先验处理策略发送到样本测试装置组119。

公开(公告)号：US09194876B2

公开(公告)日：2015-11-24

申请号：US12729787

申请日：2010-03-23

申请人： Tatsuya Tokunga ,  Naomi Ishii ,  Takashi Noguchi ,  Masaki Takano ,  Yayoi Shitara

发明人： Tatsuya Tokunga ,  Naomi Ishii ,  Takashi Noguchi ,  Masaki Takano ,  Yayoi Shitara

IPC分类号： G01N1/28 ,  G01N1/02 ,  G01P15/16 ,  G01F3/00 ,  G01N35/00

CPC分类号： G01N35/0092 ,  G01N35/0095 ,  G01N35/02 ,  G01N2035/00881 ,  G01N2035/0091 ,  G01N2035/0094 ,  G01N2035/0406 ,  G06F19/00 ,  G16H10/00 ,  Y02A90/22 ,  Y02A90/26

摘要： A management server of a sample inspection system includes sample processing information generated on the basis of inspection request data, facility data, a simulation execution portion and a window generation portion for generating a monitor window. The inspection request data contains a priority, an order time, a required time and inspection items and the sample processing information contains an inspection start time and an inspection estimate finish time. The monitor window has a work area in which the samples represented by sample bars parallel to the abscissa are arranged in a vertical direction and a past record and a future schedule are allocated to this abscissa with the present time as the base. The sample bars display a simulation execution portion for executing simulation on the basis of the inspection start time, the inspection estimate finish time and a delay time. The management server displays the simulation result.

摘要翻译： 样本检查系统的管理服务器包括基于检查请求数据生成的样本处理信息，设施数据，模拟执行部分和用于生成监视器窗口的窗口生成部分。 检查请求数据包含优先权，订单时间，所需时间和检查项目，并且样本处理信息包含检查开始时间和检查估计完成时间。 监视器窗口具有工作区域，其中与横坐标平行的样本条表示的样本在垂直方向上排列，并且将过去记录和未来调度以当前时间作为基准分配给该横坐标。 样品条显示用于基于检查开始时间，检查估计完成时间和延迟时间来执行模拟的模拟执行部分。 管理服务器显示仿真结果。

公开(公告)号：US08723181B2

公开(公告)日：2014-05-13

申请号：US12662272

申请日：2010-04-08

申请人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Kyung-bae Park

发明人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Kyung-bae Park

IPC分类号： H01L29/10

CPC分类号： H01L21/02675 ,  H01L21/2026 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/12 ,  H01L27/1281

摘要： Stacked transistors and electronic devices including the stacked transistors. An electronic device includes a substrate, a first transistor on the substrate and including a first active layer, a first gate, and a first gate insulating layer between the first active layer and the first gate, a first metal line spaced apart from the first gate on the substrate, a first insulating layer covering the first transistor and the first metal line, and a second transistor on the first insulating layer between the first transistor and the first metal line, and including a second active layer, a second gate, and a second gate insulating layer between the second active layer and the second gate.

摘要翻译： 堆叠晶体管和包括堆叠晶体管的电子器件。 电子器件包括衬底，衬底上的第一晶体管，并且在第一有源层和第一栅极之间包括第一有源层，第一栅极和第一栅极绝缘层，与第一栅极间隔开的第一金属线 在所述基板上，覆盖所述第一晶体管和所述第一金属线的第一绝缘层，以及在所述第一晶体管和所述第一金属线之间的所述第一绝缘层上的第二晶体管，并且包括第二有源层，第二栅极和 第二栅极绝缘层，位于第二有源层和第二栅极之间。

公开(公告)号：US20120286668A1

公开(公告)日：2012-11-15

申请号：US13518894

申请日：2010-12-13

申请人： Kazuyoshi Kondo ,  Ryosuke Matsui ,  Terutaka Muramatsu ,  Takashi Noguchi ,  Ryo Suzuki

发明人： Kazuyoshi Kondo ,  Ryosuke Matsui ,  Terutaka Muramatsu ,  Takashi Noguchi ,  Ryo Suzuki

IPC分类号： H05B37/00

CPC分类号： H05B33/089 ,  F21K9/27 ,  F21Y2103/10 ,  F21Y2115/10 ,  Y02B20/341 ,  Y02B20/386

摘要： The object of the present invention is to provide a LED illumination system which does not cause heat generation and damage, even when a straight-tube fluorescent lamp is mistakenly fitted into a straight-tube fluorescent lamp luminaire in which the fluorescent lamp ballast has been replaced with a LED lighting device.The LED illumination system according to the present invention is configurated in such a manner that the LED lighting device is installed in an existing straight-tube fluorescent lamp luminaire, and the LED lamp is connected to the existing sockets. The characteristic of the output from the LED lighting device connected to either inter-terminal section A on the ends of the LED lamp is to be different from that of an existing fluorescent lamp lighting device. The LED lamp is provided with lighting device output detection means for detecting the output from the LED lighting device and also with protection means for cutting off the input to the LED lamp when the output detected by the lighting device output detection means is outside of a predetermined range.

摘要翻译： 本发明的目的是提供一种即使当直管式荧光灯被错误地装配到已经更换了荧光灯镇流器的直管式荧光灯灯具中时也不引起发热和损坏的LED照明系统 配有LED照明装置。 根据本发明的LED照明系统被配置为使得LED照明装置安装在现有的直管荧光灯灯具中，并且LED灯连接到现有的插座。 连接到LED灯两端的端子间部分A的LED照明装置的输出的特性与现有荧光灯照明装置的输出特性不同。 LED灯具有用于检测来自LED照明装置的输出的照明装置输出检测装置，并且还具有用于当由照明装置输出检测装置检测到的输出超出预定值时切断对LED灯的输入的保护装置 范围。

公开(公告)号：US20120075844A1

公开(公告)日：2012-03-29

申请号：US13375788

申请日：2010-06-03

申请人： Kazuya Imagi ,  Takashi Noguchi

发明人： Kazuya Imagi ,  Takashi Noguchi

IPC分类号： F21L4/00

CPC分类号： A47G23/0309 ,  F21V33/0036 ,  F21Y2115/10

摘要： An LED coaster may include: a light transmitting cover, on the upper surface of which an object is placed; a bottom cover attached to the lower surface of the light transmitting cover; a substrate provided between the light transmitting cover and the bottom cover, having an LED mounted on a component surface on the light transmitting cover side and having a switch that turns the LED on and off mounted on a solder surface on the bottom cover side; batteries contained in a battery storage part of the bottom cover to supply electric power to the LED; two rubber pads attached to the bottom surface of the bottom cover; and a switch pad that is attached to the inside of the bottom cover in a vertically moveable manner and on which a switch pressing part facing the switch is arranged. The two rubber pads and the switch pad may be arranged near the outer periphery of the bottom of the bottom cover at approximately equal intervals in a circumferential direction, and the diameter of the switch pad may be set to just under ½ of the diameter of the LED coaster.

摘要翻译： LED过山车可以包括：透光罩，其上表面放置有物体; 底盖附接到透光罩的下表面; 设置在所述透光罩和所述底盖之间的基板，具有安装在所述透光罩侧的部件表面上的LED，并且具有使安装在所述底盖侧的焊料表面上的LED接通和断开的开关; 包含在底盖的电池存储部分中的电池以向LED提供电力; 两个橡胶垫连接到底盖底面; 以及以垂直移动的方式安装在底盖的内部并且布置有面向开关的开关按压部的开关垫。 两个橡胶垫和开关垫可以沿圆周方向以大致相等的间隔设置在底盖的底部的外周附近，并且开关垫的直径可以设定在直径的1/2以下 LED过山车。

公开(公告)号：US08022408B2

公开(公告)日：2011-09-20

申请号：US12659776

申请日：2010-03-22

申请人： Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-Young Kim ,  Huaxiang Yin ,  Xiaoxin Zhang

发明人： Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-Young Kim ,  Huaxiang Yin ,  Xiaoxin Zhang

IPC分类号： H01L29/04

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/814 ,  Y10S977/90 ,  Y10S977/932 ,  Y10S977/943

摘要： Example embodiments relate to a crystalline nanowire substrate having a structure in which a crystalline nanowire film having a relatively fine line-width may be formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the crystalline nanowire substrate may include preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.

摘要翻译： 示例性实施例涉及具有其中可以在基板上形成具有相对较细的线宽的结晶纳米线膜的结构的晶体纳米线基板及其制造方法，以及使用其制造薄膜晶体管的方法 。 制造结晶纳米线基板的方法可以包括制备基板，在基板上形成绝缘膜，在绝缘膜上形成硅膜，将绝缘膜和硅膜图案化成带状，减小线宽 绝缘膜通过底切蚀刻绝缘膜的至少一个侧面，并且通过使硅膜熔化和结晶而在绝缘膜的上表面上形成自对准硅纳米线膜。

公开(公告)号：US07768010B2

公开(公告)日：2010-08-03

申请号：US12216701

申请日：2008-07-09

申请人： Do-young Kim ,  Takashi Noguchi

发明人： Do-young Kim ,  Takashi Noguchi

IPC分类号： H01L31/0376 ,  H01L31/20 ,  H01L21/00

CPC分类号： H01L27/124 ,  H01L29/42384

摘要： Provided are a poly crystalline silicon semiconductor device and a method of fabricating the same. Portions of a silicon layer except for gates are removed to reduce a parasitic capacitance caused from the silicon layer existing on gate bus lines. The silicon layer exists under the gates only, thus the parasitic capacitance is reduced and the deterioration and the delay of signals are prevented. Accordingly, the poly crystalline silicon semiconductor device, such as a thin film transistor, has excellent electric characteristics.

摘要翻译： 提供一种多晶硅半导体器件及其制造方法。 除去栅极以外的硅层的部分被去除以减少由存在于栅极总线上的硅层引起的寄生电容。 硅层仅存在于栅极之下，因此寄生电容减小，并且防止信号的劣化和延迟。 因此，诸如薄膜晶体管的多晶硅半导体器件具有优异的电特性。

公开(公告)号：US07723168B2

公开(公告)日：2010-05-25

申请号：US11283874

申请日：2005-11-22

申请人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Kyung-bae Park

发明人： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Kyung-bae Park

IPC分类号： H01L21/00

CPC分类号： H01L21/02675 ,  H01L21/2026 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/12 ,  H01L27/1281

摘要： A method of manufacturing a polycrystalline Si film and a method of manufacturing a stacked transistor are provided. The method of manufacturing the polycrystalline Si film includes preparing an insulating substrate on which is formed a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate, sequentially formed, forming an interconnection metal line separated from the gate, forming an insulating layer that covers the transistor and the interconnection metal line, forming an amorphous silicon layer on the insulating layer; and annealing the amorphous silicon layer.

摘要翻译： 提供一种制造多晶Si膜的方法和制造堆叠晶体管的方法。 制造多晶Si膜的方法包括制备绝缘基板，其上形成有依次形成的多晶硅，具有多晶硅有源层，栅极绝缘层和栅极，形成与栅极分离的互连金属线， 形成覆盖晶体管和互连金属线的绝缘层，在绝缘层上形成非晶硅层; 并退火非晶硅层。