公开(公告)号：US20170083471A1

公开(公告)日：2017-03-23

申请号：US15367218

申请日：2016-12-02

Applicant: The Regents of the University of Michigan

Inventor： Supreet JELOKA ,  Sandunmalee Nilmini ABEYRATNE ,  Ronald George DRESLINSKI ,  Reetuparna DAS ,  Trevor Nigel MUDGE ,  David Theodore BLAAUW

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4022 ,  G06F13/1642 ,  G06F13/374 ,  G06F2213/0038 ,  G11C7/10 ,  G11C7/1012 ,  H03K17/693

Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).

公开(公告)号：US20140181581A1

公开(公告)日：2014-06-26

申请号：US14098821

申请日：2013-12-06

Applicant: The Regents of the University of Michigan ,  ARM Limited

Inventor： Krisztian FLAUTNER ,  Todd Michael AUSTIN ,  David Theodore BLAAUW ,  Trevor Nigel MUDGE ,  David BULL

IPC: G06F11/14

CPC classification number: G06F11/0793 ,  G06F11/00 ,  G06F11/0706 ,  G06F11/0736 ,  G06F11/0754 ,  G06F11/0757 ,  G06F11/079 ,  G06F11/1402 ,  G06F11/1604

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

公开(公告)号：US20140013178A1

公开(公告)日：2014-01-09

申请号：US13926213

申请日：2013-06-25

Applicant: The Regents of the University of Michigan ,  ARM Limited

Inventor： Krisztian FLAUTNER ,  Todd Michael AUSTIN ,  David Theodore BLAAUW ,  Trevor Nigel MUDGE ,  David BULL

IPC: G06F11/16

CPC classification number: G06F11/0793 ,  G06F11/00 ,  G06F11/0706 ,  G06F11/0736 ,  G06F11/0754 ,  G06F11/0757 ,  G06F11/079 ,  G06F11/1402 ,  G06F11/1604

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract translation: 集成电路包括具有错误检测和误差校正电路的一个或多个部分，并且其操作参数给出有限的非零误码率以及形成和操作以提供零错误率的一个或多个部分。

公开(公告)号：US20160034339A1

公开(公告)日：2016-02-04

申请号：US14880878

申请日：2015-10-12

Applicant: ARM Limited ,  The Regents of the University of Michigan

Inventor： Krisztian FLAUTNER ,  Todd Michael AUSTIN ,  David Theodore BLAAUW ,  Trevor Nigel MUDGE ,  David BULL

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/00 ,  G06F11/0706 ,  G06F11/0736 ,  G06F11/0754 ,  G06F11/0757 ,  G06F11/079 ,  G06F11/1402 ,  G06F11/1604

Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Abstract translation: 集成电路包括具有错误检测和误差校正电路的一个或多个部分，并且其操作参数给出有限的非零误码率以及形成和操作以提供零错误率的一个或多个部分。