公开(公告)号：US07262093B2

公开(公告)日：2007-08-28

申请号：US10891076

申请日：2004-07-15

Applicant: Tings Wang

Inventor： Tings Wang

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

Abstract: A flash memory cell is provided. The flash memory cell includes a substrate having a source and a drain formed therein, a bit line contact formed above the drain, a control gate formed above the substrate, a spacer floating gate formed above the substrate and adjacent to the control gate, and a first spacer formed between the bit line contact and the control gate, wherein the first spacer is in contact with both the bit line contact and the control gate.

Abstract translation: 提供闪存单元。 闪存单元包括其上形成有源极和漏极的衬底，形成在漏极上方的位线接触件，形成在衬底上方的控制栅极，形成在衬底上并与控制栅极相邻的间隔物浮动栅极，以及 第一间隔件形成在位线接触件和控制栅极之间，其中第一间隔件与位线接触件和控制栅极接触。

公开(公告)号：US5837578A

公开(公告)日：1998-11-17

申请号：US895107

申请日：1997-07-16

Applicant: Der-Tsyr Fan ,  Jyh-Min Tsaur ,  Chon-Shin Jou ,  Tings Wang

Inventor： Der-Tsyr Fan ,  Jyh-Min Tsaur ,  Chon-Shin Jou ,  Tings Wang

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A trenched stack-capacitor applied in a memory unit is formed through a simple process of manufacturing a stack capacitor with high density. The process includes steps of: a) forming a contact window in the insulator for exposing a cell contact of the device; b) forming a first conducting layer over the insulator and on side-walls and a base of the contact window; c) forming an etching sacrificial layer over the first conducting layer and in the contact window; d) forming an etching masking layer over a portion of the etching sacrificial layer; e) forming a plural cylindrical etching sacrificial areas by removing an another portion of the etching sacrificial layer while retaining the etching sacrificial layer under the etching masking layer; f) forming a second conducting layer on the top of the etching masking layer, on side walls of the plural cylindrical etching sacrificial areas, over the first conducting layer and in the contact window; g) removing the plural cylindrical etching sacrificial areas while retaining the first conducting layer and the second conducting layer to form a first capacitor plate; h) forming a dielectric layer on the top of the first conducting layer and on the top and side walls of the second conducting layer; and i) forming a third conducting layer over the dielectric layer to serve as a second capacitor plate.

Abstract translation: 施加在存储器单元中的沟槽叠层电容器通过制造高密度堆叠电容器的简单工艺形成。 该方法包括以下步骤：a）在绝缘体中形成接触窗口，用于暴露设备的电池接触; b）在所述绝缘体上以及所述接触窗的侧壁和底座上形成第一导电层; c）在所述第一导电层上和所述接触窗中形成蚀刻牺牲层; d）在蚀刻牺牲层的一部分上形成蚀刻掩模层; e）通过去除蚀刻牺牲层的另一部分同时将蚀刻牺牲层保持在蚀刻掩模层下方而形成多个圆柱形蚀刻牺牲区域; f）在所述蚀刻掩模层的顶部，在所述多个圆柱形蚀刻牺牲区域的侧壁上，在所述第一导电层和所述接触窗口之上形成第二导电层; g）在保留第一导电层和第二导电层以形成第一电容器板的同时，去除多个圆柱形蚀刻牺牲区域; h）在第一导电层的顶部和第二导电层的顶壁和侧壁上形成电介质层; 以及i）在所述电介质层上形成第三导电层以用作第二电容器板。

公开(公告)号：US06417099B1

公开(公告)日：2002-07-09

申请号：US09148050

申请日：1998-09-03

Applicant: Chung-Shih Tsai ,  Der-Tgyr Fan ,  Chou-Shin Jou ,  Tings Wang

Inventor： Chung-Shih Tsai ,  Der-Tgyr Fan ,  Chou-Shin Jou ,  Tings Wang

IPC: H07L2128

CPC classification number: H01L21/76877 ,  H01L21/28525

Abstract: The present invention provides a method for controlling dopant density of a plug-shaped doped polysilicon layer formed within a plug-shaped recess to prevent the dopant contained in the plug-shaped doped polysilicon layer from diffusing into a conductive layer under the plug-shaped recess through a bottom side of the plug-shaped recess, the plug-shaped recess being formed within a dielectric layer which is positioned above the conductive layer, the method comprising: (1) forming an undoped silicon layer on the surface of the plug-shaped recess; (2) forming a doped polysilicon layer on top of the undoped silicon layer to fill the plug-shaped recess; and (3) performing a thermal treatment to the semiconductor wafer so as to make the doped poly-silicon layer interact with the undoped silicon layer inside the plug-shaped recess which forms a completely doped polysilicon layer within the plug-shaped recess.

Abstract translation: 本发明提供了一种用于控制形成在插塞状凹部内的插塞状掺杂多晶硅层的掺杂剂密度的方法，以防止包含在插塞状掺杂多晶硅层中的掺杂剂扩散到插塞形凹部下方的导电层 通过插塞形凹部的底侧，插塞形凹槽形成在位于导电层上方的电介质层内，该方法包括：（1）在插塞形状的表面上形成未掺杂的硅层 休息 （2）在未掺杂的硅层的顶部上形成掺杂多晶硅层以填充插塞状凹部; 和（3）对所述半导体晶片进行热处理，以使所述掺杂多晶硅层与在所述插塞形凹部内形成完全掺杂多晶硅层的所述插塞形凹槽内的未掺杂硅层相互作用。

公开(公告)号：US6133155A

公开(公告)日：2000-10-17

申请号：US198308

申请日：1998-11-23

Applicant: Lin Tsai-Sen ,  Chou-Shin Jou ,  Tings Wang ,  Chin-Kang Li

Inventor： Lin Tsai-Sen ,  Chou-Shin Jou ,  Tings Wang ,  Chin-Kang Li

IPC: G03F7/42 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/3065

CPC classification number: H01L21/02071 ,  G03F7/42 ,  G03F7/427

Abstract: The present invention provides a method for preventing corrosion of an aluminum-containing metallic layer having a plurality of trenches on the surface of a semiconductor chip caused by chlorine atoms residing on side walls of the trenches of the metallic layer after a trench etching process. The method comprises the following steps: (1) removing the photo resistance layer on top of the metallic layer by ashing at temperatures between 178.degree. C. and 200.degree. C. after a trench etching process, (2) using an acidic solution comprising hydroxylamine (NH.sub.2 OH), hydroquinone C.sub.6 H.sub.4 (OH).sub.2, monoethanolanine (HOCH.sub.2 CH.sub.2 NH.sub.2) and water to wash off residues on the surface of the semiconductor chip, and (3) heating the semiconductor chip for a predetermined time period at temperatures between 200.degree. C. and 250.degree. C. so as to completely dissipate the chlorine atoms resided on the side walls of the metallic layer for preventing recurrent corrosion of an aluminum-containing metallic layer.

Abstract translation: 本发明提供了一种在沟槽蚀刻工艺之后，由位于金属层的沟槽的侧壁上的氯原子引起的在半导体芯片的表面上具有多个沟槽的含铝金属层的腐蚀的方法。 该方法包括以下步骤：（1）在沟槽蚀刻工艺之后，在178℃至200℃之间的温度下，通过灰化除去金属层顶部的光电层，（2）使用包含羟胺的酸性溶液 （NH 2 OH），氢醌C 6 H 4（OH）2，单乙醇化（HOCH 2 CH 2 NH 2）和水，以清洗半导体芯片表面上的残留物，和（3）在200℃至200℃的温度下加热半导体芯片预定时间 250℃，以便完全消散存在于金属层的侧壁上的氯原子，以防止含铝金属层的反复腐蚀。

公开(公告)号：US20060011966A1

公开(公告)日：2006-01-19

申请号：US10891076

申请日：2004-07-15

Applicant: Tings Wang

Inventor： Tings Wang

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

Abstract: A flash memory cell is provided. The flash memory cell includes a substrate having a source and a drain formed therein, a bit line contact formed above the drain, a control gate formed above the substrate, a spacer floating gate formed above the substrate and adjacent to the control gate, and a first spacer formed between the bit line contact and the control gate, wherein the first spacer is in contact with both the bit line contact and the control gate.

Abstract translation: 提供闪存单元。 闪存单元包括其上形成有源极和漏极的衬底，形成在漏极上方的位线接触件，形成在衬底上方的控制栅极，形成在衬底上并与控制栅极相邻的间隔物浮动栅极，以及 第一间隔件形成在位线接触件和控制栅极之间，其中第一间隔件与位线接触件和控制栅极接触。

公开(公告)号：US06492188B1

公开(公告)日：2002-12-10

申请号：US09265962

申请日：1999-03-11

Applicant: Tsai-Sen Lin ,  Bor-Shiun Wu ,  Chou-Shin Jou ,  Tings Wang

Inventor： Tsai-Sen Lin ,  Bor-Shiun Wu ,  Chou-Shin Jou ,  Tings Wang

IPC: G01R3126

CPC classification number: H01L22/24

Abstract: The present invention relates to a monitor method for quality of metal Antireflection Coating (ARC) layer and, more particularly, to a fast and accurate monitor method for quality of metal ARC layer. By using of immersing a silicon wafer comprising an ARC layer into an acidic (such as a developer) or an alkalescent solution for about 200-300 seconds, according to the present invention, at weak points of the metal ARC layer there occur voids (defects) due to a Galvanic cell effect enhanced by these chemical solutions and then how many defects can be counted by a wafer defect inspector such as a KLA instrument so that quality of the metal ARC layer can be monitored by this defect number. Besides, Since the silicon wafer used as a sample for the wafer defect inspector simply comes from a production line, i.e. a developing process, rather than from other additional processing, said method allows for fast and accurately monitoring quality of the metal ARC layers.

Abstract translation: 金属防反射涂层（ARC）层的质量监测方法技术领域本发明涉及金属防反射涂层（ARC）层的质量监测方法，更具体地说，涉及金属ARC层质量的快速准确的监测方法。 通过根据本发明，将包含ARC层的硅晶片浸入酸性（例如显影剂）或碱性溶液中约200-300秒，在金属ARC层的弱点处发生空隙（缺陷 ）由于这些化学溶液增强的电化学电池效应，然后可以通过诸如KLA仪器的晶片缺陷检查器计数多少个缺陷，以便可以通过该缺陷数来监测金属ARC层的质量。 此外，由于用作晶片缺陷检查器的样品的硅晶片简单地来自生产线，即显影过程，而不是来自其他附加处理，所述方法允许快速且准确地监测金属ARC层的质量。