-
公开(公告)号：US06996765B2
公开(公告)日：2006-02-07
申请号：US10259099
申请日：2002-09-27
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/3723 , H03M13/3972 , H03M13/658
摘要： This invention describes implementation approaches for sliding window turbo decoders. Sliding windows are used for both the beta and alpha state metric calculations. Initialization of the beta/alpha prolog sections with data from a previous iteration is employed in conjunction with a reduced length prolog section. For subsequent sliding windows the trellis values of the prolog sections are dynamically initialized based upon data derived from the signal to noise ratio of the calculated extrinsic data or the difference between the two most probable trellis states.
-
公开(公告)号：US06775801B2
公开(公告)日：2004-08-10
申请号：US10202509
申请日：2002-07-24
IPC分类号： H03M1300
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/6586
摘要： This invention presents a unique implementation of the extrinsic block the turbo decoder that solves the problem of generation and use of precision extension and normalization in the alpha and beta metrics blocks. Both alpha metric inputs and beta metric inputs are processed via a circle boundary detector indicating the quadrant of the two's complement input and a precision extend block receiving an input and a corresponding circle boundary input. An extrinsics block includes a two's complement adder of the precision extended alpha and beta metrics inputs. The proposed solution obviates the need for normalization in the alpha and beta metric blocks.
摘要翻译： 本发明提供了解决在α和β度量块中精确扩展和归一化的生成和使用问题的turbo解码器的外在块的独特实现。 Alpha公制输入和β度量输入均通过圆边界检测器进行处理，该边界检测器指示二进制补码输入的象限和接收输入的精度扩展块以及相应的圆形边界输入。 一个二进制块包括精度扩展的alpha和beta度量输入的二进制补码加法器。 所提出的解决方案消除了对α和β度量块的归一化的需要。
-
3.发明授权Reconfigurable chip level equalizer architecture for multiple antenna systems 有权用于多天线系统的可重构芯片级均衡器架构公开(公告)号：US07561618B2
公开(公告)日：2009-07-14
申请号：US11105755
申请日：2005-04-14
申请人： Antonio F. Mondragon-Torres , Steven P. Pekarich , Timothy M. Schmidl , Aris Papasakellariou , Anand G. Dabak , Eko N. Onggosanusi , Manish Goel
发明人： Antonio F. Mondragon-Torres , Steven P. Pekarich , Timothy M. Schmidl , Aris Papasakellariou , Anand G. Dabak , Eko N. Onggosanusi , Manish Goel
IPC分类号： H03H7/30
CPC分类号： H04L25/03019 , H04B1/7105 , H04B1/7117 , H04B7/0837 , H04L2025/03509 , H04L2025/03566 , H04L2025/03617
摘要： A system comprising a plurality of adaptive equalizers adapted to couple to a plurality of receive antennas, each of the antennas capable of receiving a multipath delay profile estimate (MDPE), control logic interconnecting at least some of the adaptive equalizers, and a control mechanism that, according to different MDPEs, configures at least some of the adaptive equalizers and control logic.
摘要翻译： 一种系统，包括适于耦合到多个接收天线的多个自适应均衡器，所述天线中的每一个能够接收多径延迟分布估计（MDPE），互连所述自适应均衡器中的至少一些的控制逻辑，以及控制机制， 根据不同的MDPE，配置至少一些自适应均衡器和控制逻辑。
-
公开(公告)号：US08135057B2
公开(公告)日：2012-03-13
申请号：US10699707
申请日：2003-11-03
申请人： Antonio F. Mondragon-Torres , Steven P. Pekarich , Timothy M. Schmidl , Gibong Jeong , Aris Papasakellariou , Anand G. Dabak , Eko N. Onggosanusi
发明人： Antonio F. Mondragon-Torres , Steven P. Pekarich , Timothy M. Schmidl , Gibong Jeong , Aris Papasakellariou , Anand G. Dabak , Eko N. Onggosanusi
IPC分类号： H03H7/30
CPC分类号： H04L25/03006 , H04B1/7103 , H04B1/7117 , H04B2201/7071 , H04L25/03987 , H04L2025/03401 , H04L2025/0342 , H04L2025/03509 , H04L2025/03535
摘要： A reconfigurable chip level equalizer having circuitry that restores signal orthogonality and eliminates channel interference for a wireless transmitted signal. In at least some embodiments, the reconfigurable chip level equalizer comprises two or more adaptive equalizers, a plurality of operational blocks that interconnect the two or more adaptive equalizers, and a control mechanism that configures the two or more adaptive equalizers and operational blocks according to different signal delay profiles.
摘要翻译： 具有恢复信号正交性并消除无线发射信号的信道干扰的电路的可重新配置的芯片级均衡器。 在至少一些实施例中，可重新配置的芯片级均衡器包括两个或多个自适应均衡器，互连两个或多个自适应均衡器的多个操作块，以及根据不同的配置两个或多个自适应均衡器和操作块的控制机制 信号延迟分布。
-
-
-
搜索结果
4 条记录 (耗时 0.019 秒)
