公开(公告)号：US06775801B2

公开(公告)日：2004-08-10

申请号：US10202509

申请日：2002-07-24

申请人： Tod D. Wolf ,  Antonio F. Mondragon-Torres

发明人： Tod D. Wolf ,  Antonio F. Mondragon-Torres

IPC分类号： H03M1300

CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/6586

摘要： This invention presents a unique implementation of the extrinsic block the turbo decoder that solves the problem of generation and use of precision extension and normalization in the alpha and beta metrics blocks. Both alpha metric inputs and beta metric inputs are processed via a circle boundary detector indicating the quadrant of the two's complement input and a precision extend block receiving an input and a corresponding circle boundary input. An extrinsics block includes a two's complement adder of the precision extended alpha and beta metrics inputs. The proposed solution obviates the need for normalization in the alpha and beta metric blocks.

摘要翻译： 本发明提供了解决在α和β度量块中精确扩展和归一化的生成和使用问题的turbo解码器的外在块的独特实现。 Alpha公制输入和β度量输入均通过圆边界检测器进行处理，该边界检测器指示二进制补码输入的象限和接收输入的精度扩展块以及相应的圆形边界输入。 一个二进制块包括精度扩展的alpha和beta度量输入的二进制补码加法器。 所提出的解决方案消除了对α和β度量块的归一化的需要。

公开(公告)号：US06996765B2

公开(公告)日：2006-02-07

申请号：US10259099

申请日：2002-09-27

申请人： Tod D. Wolf ,  Antonio F. Mondragon-Torres ,  Alan Gatherer

发明人： Tod D. Wolf ,  Antonio F. Mondragon-Torres ,  Alan Gatherer

IPC分类号： H03M13/00 ,  H03M13/03 ,  H04L27/06

CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3972 ,  H03M13/658

摘要： This invention describes implementation approaches for sliding window turbo decoders. Sliding windows are used for both the beta and alpha state metric calculations. Initialization of the beta/alpha prolog sections with data from a previous iteration is employed in conjunction with a reduced length prolog section. For subsequent sliding windows the trellis values of the prolog sections are dynamically initialized based upon data derived from the signal to noise ratio of the calculated extrinsic data or the difference between the two most probable trellis states.

公开(公告)号：US06993704B2

公开(公告)日：2006-01-31

申请号：US10141416

申请日：2002-05-08

申请人： Tod D. Wolf

发明人： Tod D. Wolf

IPC分类号： H03M13/03

CPC分类号： H03M13/3905 ,  H03M13/2975 ,  H03M13/3972 ,  H03M13/41 ,  H03M13/6505 ,  H03M13/6566

摘要： The concurrent memory control turbo decoder solution of this invention uses a single port main memory and a simplified scratch memory. This approach uses an interleaved forward-reverse addressing which greatly relieves the amount of memory required. This approach is in marked contrast to conventional turbo decoders which employ either a dual port main memory or a single port main memory in conjunction with a complex ping-ponged scratch memory. In the system of this invention, during each cycle accomplishes one read and one write operation in the scratch memories. If a particular location in memory, has been read, then that location is free. The next write cycle can use that location to store its data. Similarly a simplified beta RAM is implemented using a unique addressing scheme which also obviates the need for a complex ping-ponged beta RAM.

公开(公告)号：US06725409B1

公开(公告)日：2004-04-20

申请号：US09607773

申请日：2000-06-30

申请人： Tod D. Wolf

发明人： Tod D. Wolf

IPC分类号： H03M1300

CPC分类号： H03M13/3922 ,  H03M13/2957 ,  H03M13/6569

摘要： The addition of a specialized instruction to perform the MAX star function provides a way to get better performance turbo decoding on a digital signal processor. A subtractor forms the difference between inputs A and B. The sign of this difference controls a multiplexer selection of the max function maximum of inputs A and B. The difference is applied to a lookup table built to handle both positive and negative inputs. The look up table output is summed with with the difference to form the MAX star result. The size of the lookup table is selected to match the required resolution.

摘要翻译： 添加专门的指令来执行MAX星形功能，可以提供一种在数字信号处理器上获得更好的Turbo解码性能的方法。 减法器形成输入A和B之间的差异。该差异的符号控制输入A和B的最大函数最大值的多路复用器选择。该差异应用于构建为处理正输入和负输入的查找表。 查询表输出与差异相加形成MAX星形结果。 选择查找表的大小以匹配所需的分辨率。

公开(公告)号：US20090254718A1

公开(公告)日：2009-10-08

申请号：US12399719

申请日：2009-03-06

申请人： Eric Biscondi ,  David J. Hoyle ,  Tod D. Wolf

发明人： Eric Biscondi ,  David J. Hoyle ,  Tod D. Wolf

IPC分类号： G06F15/76 ,  G06F12/06 ,  G06F12/00 ,  G06F9/02

CPC分类号： G06F15/7857 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3885

摘要： A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.

摘要翻译： 根据具有本地存储器的集群架构的数字信号处理器（DSP）协处理器。 架构中的每个集群包括多个子集群，每个子集群能够执行一个或两个指令，这些指令可以专门针对特定的DSP操作。 每个集群中的子集群通过集群中的交叉开关与全局内存资源进行通信。 子集群中的一个或多个具有专用本地存储器，其可以以随机存取方式，向量存取方式或以流或堆栈方式访问。 本地存储器被布置为多个存储体。 响应于某些向量访问指令，可以根据存储在寄存器中的置换模式，在写入之前在存储体之间排列输入数据，或者在从存储体读取之后被置换。

公开(公告)号：US20090049367A1

公开(公告)日：2009-02-19

申请号：US11839845

申请日：2007-08-16

申请人： Tod D. Wolf

发明人： Tod D. Wolf

IPC分类号： H03M13/07

CPC分类号： H03M13/4169

摘要： This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations that depend on the last active add-compare-select unit a cascade block of the state metric update process. This last active add-compare-select unit controls selection of T counter signals used in the decode.

摘要翻译： 本发明提供了针对所有约束长度和帧大小获得正确的维特比解码回溯起始索引。 取决于最后一个活动的加法比较选择单元的状态度量更新过程的级联块的反向转置操作。 最后一个活动的加法比较选择单元控制在解码中使用的T计数器信号的选择。

公开(公告)号：US06209114B1

公开(公告)日：2001-03-27

申请号：US09087584

申请日：1998-05-29

申请人： Tod D. Wolf ,  Jonathan H. Shiell

发明人： Tod D. Wolf ,  Jonathan H. Shiell

IPC分类号： H03M1300

CPC分类号： H03M13/6569 ,  H03M13/1515 ,  H03M13/1545

摘要： A programmable logic device, such as a digital signal processor (DSP) (130), having a Chien search unit (116) is disclosed. The Chien search unit (116) is arranged to perform finite field arithmetic functions useful in identifying roots of a polynomial, as is useful in Reed-Solomon decoding, particularly, after the execution of a Euclidean array function. Galois field multipliers (306) perform finite field multiplication of coefficient values (&Lgr;) and powers of symbol values (&agr;); the products of such multiplications are written into the coefficient register (304) for use in connection with the next symbol value. Finite field adders (308, 310; 318, 320) produce a final sum that is interrogated by zero detection circuitry (206) to determine whether a root is presented by the current symbol value. The provision of a Chien search execution unit (116) provides important efficiency so as to enable programmable logic devices, such as digital signal processors (130) and microprocessors to effect Reed-Solomon decoding.

摘要翻译： 公开了一种具有Chien搜索单元（116）的可编程逻辑器件，例如数字信号处理器（DSP）130。 Chien搜索单元（116）被布置为执行有用的字段算术功能，用于识别多项式的根，这在Reed-Solomon解码中是有用的，特别是在执行欧几里得数组函数之后。 伽罗瓦域乘法器（306）执行系数值（LAMBD）和符号值（α）的幂的有限域乘法; 这种乘法的乘积被写入系数寄存器（304），以便与下一个符号值一起使用。 有限场加法器（308,310; 318,320）产生由零检测电路（206）询问的最终和，以确定根是否由当前符号值呈现。 提供Chien搜索执行单元（116）提供了重要的效率，以便使诸如数字信号处理器（130）和微处理器之类的可编程逻辑器件能够实现Reed-Solomon解码。

公开(公告)号：US6154869A

公开(公告)日：2000-11-28

申请号：US200488

申请日：1998-11-25

申请人： Tod D. Wolf

发明人： Tod D. Wolf

IPC分类号： H03M13/15 ,  H03M13/00

CPC分类号： H03M13/158 ,  H03M13/15 ,  H03M13/1515

摘要： A combined Chien search and error position circuit (116), for use in Reed-Solomon decoding, is disclosed. The circuit (116) operates in response to a zero signal (ZRO) issued by a root detection block (200) that iteratively evaluates an error locator polynomial .LAMBDA.(x) over the Galois field used in the coding. A zeroes register (218) and a position register (22) are provided, each of which have a plurality of stages (218.sub.0 through 218.sub.t ; 220.sub.0 through 220.sub.t). An index counter (208) maintains a count over the Galois field, corresponding to the Galois field element under evaluation in the root detection block (200). An exponentiation circuit (212) performs a Galois field exponentiation of the count, and applies the result to the inputs of each of the zeroes register stages (218.sub.0 through 218.sub.t); the count is subtracted from the maximum Galois field index (e.g., from 255 for Galois field 256) and, for all but the zeroth iteration, the difference is applied to the inputs of each of the position register stages (220.sub.0 through 220.sub.t). A root counter (207) maintains a count of the number of roots identified by the root detection block (200), which is used to sequentially select the register stages (218.sub.0 through 218.sub.t ; 220.sub.0 through 220.sub.t) into which the zeroes and position values are stored.

摘要翻译： 公开了用于Reed-Solomon解码的组合Chien搜索和错误位置电路（116）。 电路（116）响应于根检测块（200）发出的零信号（ZRO），该根信号检测块（200）在编码中使用的伽罗瓦域迭代地计算错误定位多项式LAMBDA（x）。 提供零寄存器（218）和位置寄存器（22），每个寄存器具有多个级（2180至218t; 2200至220t）。 索引计数器（208）保持与根路检测块（200）中正在评估的伽罗瓦域元素相对应的伽罗瓦域的计数。 求幂电路（212）执行计数的伽罗瓦域取幂，并将结果应用于零寄存器级（2180至218t）中的每一个的输入; 从最大伽罗瓦域索引（例如，对于伽罗瓦域256为255）减去计数，并且对于除第零迭代之外的所有值，差值被施加到每个位置寄存器级（2200至220t）的输入。 根计数器（207）保持由根检测块（200）识别的根数的计数，其用于顺序地选择零和位置值为其中的寄存器级（2180至218t; 2200至220t） 存储。

公开(公告)号：US5951677A

公开(公告)日：1999-09-14

申请号：US086997

申请日：1998-05-29

申请人： Tod D. Wolf ,  Jonathan H. Shiell

发明人： Tod D. Wolf ,  Jonathan H. Shiell

IPC分类号： G06F9/34 ,  G06F9/345 ,  G06F12/02

CPC分类号： G06F9/3897 ,  G06F9/30007 ,  H03M13/1535 ,  H03M13/1545 ,  H04L1/0052 ,  H04L1/0057

摘要： A programmable logic device, such as a digital signal processor (DSP) (130), having a Euclidean array unit (115; 115') is disclosed. The Euclidean array unit (115; 115') is arranged to perform finite field arithmetic functions useful in determining the greatest common factor among two polynomial series, in a sequential fashion beginning with a highest order pair of operands (A.sub.0, B.sub.0) and proceeding along the sequence. A source register (SRC) receives each pair of operands, and the results are stored in a result register (RES) in reverse order, prior to writing the results in memory. As a result, B result values are stored in the same location as the A input operand, and vice versa. This reversal of memory locations permits successive passes of the Euclidean operation to be carried out with simple incrementing of the starting byte address (SBA) at which the operands are located in memory, thus eliminating the need for large memory shifts. The Euclidean array unit (115') may also operate upon more than one A and B input operand at a time, for further efficiency.

摘要翻译： 公开了一种具有欧几里德阵列单元（115; 115'）的可编程逻辑器件，例如数字信号处理器（DSP）（130）。 欧几里德阵列单元（115; 115'）被布置成执行有限域算术功能，以有限的方式确定两个多项式序列中的最大公因子，以顺序方式从最高阶操作数对（A0，B0）开始，并沿着 序列。 在将结果写入存储器之前，源寄存器（SRC）接收每对操作数，结果以相反的顺序存储在结果寄存器（RE​​S）中。 结果，B结果值存储在与A输入操作数相同的位置，反之亦然。 存储器位置的这种反转允许通过简单地增加操作数位于存储器中的起始字节地址（SBA）来进行欧氏距离操作的连续通过，因此不需要大的存储器位移。 欧几里德阵列单元（115'）也可以一次对多于一个A和B输入操作数进行操作，以进一步提高效率。

公开(公告)号：US06473779B1

公开(公告)日：2002-10-29

申请号：US08725598

申请日：1996-10-03

申请人： Tod D. Wolf

发明人： Tod D. Wolf

IPC分类号： G06F700

CPC分类号： G06F7/724 ,  H03M13/151

摘要： A combinatorial polynomial multiplier for Galois Field 256 arithmetic utilizes fewer components than an iterative Galois Field 256 arithmetic multiplier and operates 8 times faster. The combinatorial multiplier employs AND and XOR functions and operates in a single clock cycle. It can reduce the number of transistors required for the Galois Field 256 arithmetic multiplier for a Reed-Solomon decoder by almost 90%.

摘要翻译： Galois Field 256算法的组合多项式乘法器比迭代Galois Field 256算术乘法器使用更少的分量，并且运算速度提高了8倍。 组合乘法器采用AND和XOR功能，并在单个时钟周期内运行。 它可以将Reed-Solomon解码器的Galois Field 256算术乘法器所需的晶体管数量减少近90％。