公开(公告)号：US20250113605A1

公开(公告)日：2025-04-03

申请号：US18496941

申请日：2023-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wan-Tien Chou ,  Gang Ren ,  Xingxing Chen ,  Ji Feng ,  Guohai Zhang

IPC: H01L21/84 ,  H01L21/8234 ,  H01L27/12

Abstract: A method for fabricating a radio-frequency (RF) device includes the steps of first providing a substrate comprising a core region and a non-core region, forming a shallow trench isolation (STI) in the substrate between the core region and the non-core region, forming a first gate oxide layer on the core region and the non-core region, forming a patterned mask on the non-core region and the STI, removing the first gate oxide layer on the core region, and then forming a second gate oxide layer on the core region.

公开(公告)号：US20240332067A1

公开(公告)日：2024-10-03

申请号：US18739344

申请日：2024-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US11127621B2

公开(公告)日：2021-09-21

申请号：US16673929

申请日：2019-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ji Feng ,  Yunfei Li ,  Guohai Zhang ,  Ching Hwa Tey ,  Jingling Wang

IPC: H01L21/762 ,  H01L21/76 ,  H01L21/311 ,  H01L21/265

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate is provided and the substrate has a first semiconductor layer formed thereon. Next, an isolating structure is formed in the first semiconductor layer, and a sacrificial layer is formed on the first semiconductor layer by consuming a top portion of the first semiconductor layer. Then, the sacrificial layer is removed to form a second semiconductor layer, and a portion of the isolating structure is also removed to form a shallow trench isolation (STI), with a top surface of the shallow trench isolation being substantially coplanar with a top surface of the second semiconductor layer.

公开(公告)号：US10332839B2

公开(公告)日：2019-06-25

申请号：US15400600

申请日：2017-01-06

Applicant: United Microelectronics Corp.

Inventor： Keen Zhang ,  Ji Feng ,  De-Jin Kong ,  Yun-Fei Li ,  Guo-Hai Zhang ,  Ching-Hwa Tey ,  Jing Feng

IPC: H01L21/00 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.

公开(公告)号：US09082660B2

公开(公告)日：2015-07-14

申请号：US13965600

申请日：2013-08-13

Applicant: United Microelectronics Corp.

Inventor： Ji Feng ,  Hai-Long Gu ,  Ying-Tu Chen

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/762

CPC classification number: H01L22/12 ,  H01L21/76205 ,  H01L21/76237 ,  H01L22/20

Abstract: A method of controlling a threshold voltage is provided. The method of controlling a threshold voltage includes performing a film-thickness measuring step to measure the thickness of a film layer on a wafer to obtain a film-thickness value. Then, at least one parameter is decided, selected, or generated according to the film-thickness value. Next, an ion implantation process is performed on the wafer, wherein the ion implantation process is executed according to the parameter to form a threshold voltage adjustment region in the wafer below the film layer.

Abstract translation: 提供了一种控制阈值电压的方法。 控制阈值电压的方法包括进行膜厚测量步骤，以测量晶片上的薄膜层的厚度以获得薄膜厚度值。 然后，根据膜厚度值决定，选择或生成至少一个参数。 接下来，在晶片上进行离子注入工艺，其中根据参数执行离子注入处理，以在薄膜层下方的晶片中形成阈值电压调整区域。

公开(公告)号：US11355389B2

公开(公告)日：2022-06-07

申请号：US17133652

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US20150050751A1

公开(公告)日：2015-02-19

申请号：US13965600

申请日：2013-08-13

Applicant: United Microelectronics Corp.

Inventor： Ji Feng ,  Hai-Long Gu ,  Ying-Tu Chen

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L21/76205 ,  H01L21/76237 ,  H01L22/20

Abstract: A method of controlling a threshold voltage is provided. The method of controlling a threshold voltage includes performing a film-thickness measuring step to measure the thickness of a film layer on a wafer to obtain a film-thickness value. Then, at least one parameter is decided, selected, or generated according to the film-thickness value. Next, an ion implantation process is performed on the wafer, wherein the ion implantation process is executed according to the parameter to form a threshold voltage adjustment region in the wafer below the film layer.

Abstract translation: 提供了一种控制阈值电压的方法。 控制阈值电压的方法包括进行膜厚测量步骤，以测量晶片上的薄膜层的厚度以获得薄膜厚度值。 然后，根据膜厚度值决定，选择或生成至少一个参数。 接下来，在晶片上进行离子注入工艺，其中根据参数执行离子注入处理，以在薄膜层下方的晶片中形成阈值电压调整区域。

公开(公告)号：US12040224B2

公开(公告)日：2024-07-16

申请号：US17737011

申请日：2022-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US20180197819A1

公开(公告)日：2018-07-12

申请号：US15400600

申请日：2017-01-06

Applicant: United Microelectronics Corp.

Inventor： Keen Zhang ,  Ji Feng ,  De-Jin Kong ,  Yun-Fei Li ,  Guo-Hai Zhang ,  Ching-Hwa Tey ,  Jing Feng

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53295 ,  H01L23/5283 ,  H01L23/53228

Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.