公开(公告)号：US20240120316A1

公开(公告)日：2024-04-11

申请号：US17989635

申请日：2022-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuang Ho ,  Yu-Jie Lin ,  Yi-Feng Hsu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/16225

Abstract: The present disclosure relates to a semiconductor package, a semiconductor bonding structure and a method of fabricating the same. The semiconductor package includes a first chip, a second chip and a conductive structure, wherein the conductive structure is disposed at a side of the second chip and over a second upper surface of the first interconnection structure to electrically connect to the first interconnection structure. The semiconductor bonding structure includes a first substrate, a plurality of first interconnection structures, a plurality of chips and a plurality of conductive structures, wherein the conductive structures are respectively disposed at a side of each of the chips and over a second upper surface of each first interconnection structure, to electrically connect to each first interconnection.

公开(公告)号：US20240429093A1

公开(公告)日：2024-12-26

申请号：US18224576

申请日：2023-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin ,  Kai-Kuang Ho ,  Chuan-Lan Lin ,  Yu-Ping Wang ,  Chu-Fu Lin ,  Yi-Feng Hsu ,  Yu-Jie Lin

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/784 ,  H01L23/544

Abstract: A method for fabricating a semiconductor device includes the steps of first defining a scribe line on a front side of a wafer, in which the wafer includes an inter-metal dielectric (IMD) layer disposed on a substrate and an alternating stack disposed on the IMD layer. Next, part of the alternating stack is removed to form a trench on the front side of the wafer, a dielectric layer is formed in the trench, and then a dicing process is performed along the scribe line from a back side of the wafer to divide the wafer into chips.

公开(公告)号：US20240120306A1

公开(公告)日：2024-04-11

申请号：US17980571

申请日：2022-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuang Ho ,  Yu-Jie Lin ,  Yi-Feng Hsu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L23/4985 ,  H01L24/08 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/08238 ,  H01L2224/32054 ,  H01L2224/32225 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/83203 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/15151 ,  H01L2924/182

Abstract: A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.