公开(公告)号：US12131796B2

公开(公告)日：2024-10-29

申请号：US18195860

申请日：2023-05-10

申请人： Rambus Inc.

发明人： Yohan Frans

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/065

CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C5/063 ,  G11C7/22 ,  G11C5/025 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311

摘要： A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

公开(公告)号：US20240339428A1

公开(公告)日：2024-10-10

申请号：US18749274

申请日：2024-06-20

申请人： Intel Corporation

发明人： Weng Hong TEH ,  Chia-Pin CHIU

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/50 ,  H01L23/538 ,  H01L25/16 ,  H01L25/18

CPC分类号： H01L24/25 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L21/568 ,  H01L23/3128 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162

摘要： Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US20240153833A1

公开(公告)日：2024-05-09

申请号：US18052567

申请日：2022-11-03

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Wu-Der YANG

IPC分类号： H01L23/13 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/13 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48221 ,  H01L2224/73215 ,  H01L2924/1436 ,  H01L2924/15151

摘要： A package structure includes a first substrate, a second substrate, a chip, a first wire and a second wire. The first substrate includes a top surface, a bottom surface, a window and a first conductive pad. The bottom surface of the first substrate is opposite to the top surface. The window communicates the top surface and the bottom surface. The first conductive pad is located over the bottom surface. The second substrate is located over the first substrate. The second substrate is spaced from the first substrate and includes a second conductive pad facing the top surface of the first substrate and exposed from the window. The chip is located over the second substrate. The first wire connects the first conductive pad to the second conductive pad. The second wire connects the second conductive pad to the third conductive pad.

公开(公告)号：US20240063067A1

公开(公告)日：2024-02-22

申请号：US17890592

申请日：2022-08-18

申请人： Micron Technology, Inc.

发明人： Jong Sik Paek

IPC分类号： H01L23/13 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/32 ,  H01L24/83 ,  H01L21/563 ,  H01L2224/83102 ,  H01L2224/8309 ,  H01L2224/83091 ,  H01L2224/16221 ,  H01L2224/32221 ,  H01L2224/73204 ,  H01L2924/1511 ,  H01L2924/15151

摘要： This document discloses techniques, apparatuses, and systems for a semiconductor device with a porous air vent. The semiconductor device includes a semiconductor die mounted to a substrate at one or more contact pads. Underfill material is disposed between the semiconductor die and the substrate. The substrate includes a porous portion composed of a porous material. The porous material is such that air, but not the underfill material, may pass from an area between the semiconductor die and the substrate to an area below the substrate. As a result, air may pass through the porous portion during the underfill process and the underfill material may be retained. Thus, voids and back contamination may be limited to assemble a reliable semiconductor device

公开(公告)号：US20240047331A1

公开(公告)日：2024-02-08

申请号：US17879125

申请日：2022-08-02

申请人： NANYA TECHNOLOGY CORPORATION

发明人： WU-DER YANG

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13 ,  H01L21/48

CPC分类号： H01L23/49833 ,  H01L24/48 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/13 ,  H01L24/73 ,  H01L24/32 ,  H01L24/33 ,  H01L21/4853 ,  H01L2924/15311 ,  H01L2224/73215 ,  H01L2224/4824 ,  H01L2924/15151 ,  H01L2924/182 ,  H01L2224/3201 ,  H01L2224/32225 ,  H01L2224/32058 ,  H01L2224/3303 ,  H01L2224/33055 ,  H01L2224/48464

摘要： A WBGA package and a method of manufacturing a WBGA package are provided. The WBGA package includes a first substrate having a first through hole and a second substrate having a second through hole over the first through hole of the first substrate. The WBGA package also includes an electronic component having an active surface over the second through hole of the second substrate.

公开(公告)号：US20240021550A1

公开(公告)日：2024-01-18

申请号：US17866732

申请日：2022-07-18

申请人： NANYA TECHNOLOGY CORPORATION

发明人： WU-DER YANG

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/48464 ,  H01L2224/48221 ,  H01L2924/35121 ,  H01L2924/182 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2224/03452 ,  H01L2224/03416 ,  H01L2224/0362 ,  H01L2224/48644 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/05644 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05573 ,  H01L2224/05008 ,  H01L2224/05017 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05076 ,  H01L2224/05083

摘要： A bonding pad structure and a method of manufacturing a bonding pad structure are provided. The bonding pad structure includes a carrier, a first conductive layer disposed over the carrier, a second conductive layer disposed on the first conductive layer and contacting the first conductive layer, and a third conductive layer disposed on the second conductive layer and contacting the second conductive layer. The bonding pad structure also includes a first passivation layer disposed on the first conductive layer and contacting at least one of the first conductive layer or the second conductive layer. An upper surface of the third conductive layer facing away from the carrier is exposed from the first passivation layer.

公开(公告)号：US11862525B2

公开(公告)日：2024-01-02

申请号：US17695757

申请日：2022-03-15

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Tsung-Yu Lin ,  Pei-Yu Wang ,  Chung-Wei Hsu

IPC分类号： H01L23/10 ,  H01L23/00 ,  H01L23/053 ,  H01L21/50 ,  H01L33/48 ,  H01L23/04 ,  G01L19/14

CPC分类号： H01L23/10 ,  H01L21/50 ,  H01L23/04 ,  H01L23/053 ,  H01L24/48 ,  H01L33/486 ,  G01L19/14 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/1659 ,  H01L2924/16195 ,  H01L2924/17151 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

公开(公告)号：US20230260887A1

公开(公告)日：2023-08-17

申请号：US17903209

申请日：2022-09-06

申请人： Samsung Electronics Co., Ltd.

发明人： Se-Ho YOU ,  Ji-Yong PARK

IPC分类号： H01L23/498 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L23/49833 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16137 ,  H01L2224/16227 ,  H01L2224/32137 ,  H01L2224/73203 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1511 ,  H01L2924/15151

摘要： A semiconductor package includes a first substrate including a first wiring layer inside the first substrate, a second substrate including a second wiring layer inside the second substrate, and a mold layer between the first substrate and the second substrate. An upper surface of the mold layer is on a same plane as upper surfaces of the first substrate and the second substrate. The package includes a first connecting film on each of the upper surface of the first substrate and the upper surface of the second substrate, the first connecting film connecting the first substrate and the second substrate, and a first semiconductor chip on the upper surface of the first substrate. The first semiconductor chip is spaced apart from the first connecting film, and an upper surface of the first connecting film is lower than an upper surface of the first semiconductor chip.

公开(公告)号：US20190104351A1

公开(公告)日：2019-04-04

申请号：US16206916

申请日：2018-11-30

申请人： Knowles Electronics, LLC

发明人： Venkataraman Chandrasekaran ,  Claus Furst ,  Joshua Watson ,  John Szczech

IPC分类号： H04R1/02 ,  B81B7/02 ,  H04R1/04 ,  H04R19/00 ,  H04R19/04 ,  H04R3/00 ,  B81B7/00 ,  B81C1/00 ,  G01L27/00 ,  G01L23/12

CPC分类号： H04R1/028 ,  B81B7/0061 ,  B81B7/02 ,  B81B2201/012 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00238 ,  G01L23/125 ,  G01L27/005 ,  H01L2224/48091 ,  H01L2924/15151 ,  H01L2924/16152 ,  H04R1/04 ,  H04R3/005 ,  H04R19/005 ,  H04R19/04 ,  H04R2201/003 ,  H04R2430/21 ,  H01L2924/00014

摘要： A microphone device comprises a microphone die including a microphone motor, an acoustic integrated circuit structured to process signals produced by the microphone motor, and a sensor die stacked on top of the acoustic integrated circuit, wherein the sensor die comprises a pressure sensor. Another microphone comprises a microphone die including a microphone motor and an integrated circuit die. The integrated circuit die comprises an acoustic integrated circuit structured to process signals produced by the microphone motor, a pressure sensor, and a pressure integrated circuit structured to press signals produced by the pressure sensor.

公开(公告)号：US20180366398A1

公开(公告)日：2018-12-20

申请号：US16006895

申请日：2018-06-13

申请人： FUJITSU LIMITED

发明人： Yuki Hoshino ,  KENJI FUKUZONO

IPC分类号： H01L23/498 ,  H01L21/48 ,  B23K1/00

CPC分类号： H01L23/49816 ,  B23K1/0016 ,  B23K1/203 ,  B23K3/0623 ,  B23K3/08 ,  B23K2101/40 ,  H01L21/4853 ,  H01L23/49838 ,  H01L2924/15151 ,  H05K1/115

摘要： A BGA package substrate includes a substrate, a resist formed over the substrate and includes an opening, a land formed over the substrate in the opening, and a solder ball fused to the land, wherein the resist includes a notch at an edge of the opening through which the land is exposed, the notch having a bottom at a position lower than a surface of the land.