公开(公告)号：US20180331063A1

公开(公告)日：2018-11-15

申请号：US16042123

申请日：2018-07-23

申请人： DOWA ELECTRONICS MATERIALS CO., LTD.

发明人： Satoru KURITA ,  Keiichi ENDOH ,  Hiromasa MIYOSHI

IPC分类号： H01L23/00 ,  B22F1/00 ,  B22F5/00 ,  B23K35/30 ,  B23K103/00 ,  B23K103/12

CPC分类号： H01L24/27 ,  B22F1/0018 ,  B22F1/0074 ,  B22F5/006 ,  B22F2999/00 ,  B23K35/3006 ,  B23K2103/12 ,  B23K2103/56 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27332 ,  H01L2224/27505 ,  H01L2224/277 ,  H01L2224/29017 ,  H01L2224/29339 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/8384 ,  H01L2924/00 ,  H01L2924/10253 ,  H01L2924/15788 ,  B22F3/22

摘要： A method for joining an electronic part, comprising: inserting a joining silver sheet between an electronic part and a substrate, to which the electronic part is to be joined; and heating them to the temperature range of TA (° C.) or higher and TB (° C.) or lower, under application of a pressure to the electronic part and the substrate to make a contact surface pressure of the electronic part and the silver sheet of from 0.5 to 3 MPa. The joining silver sheet comprises silver particles having a particle diameter of from 1 to 250 nm integrated by sintering, and has a capability of further undergoing sintering on heating and retaining the silver sheet at a temperature range of “TA (° C.) or higher and TB (° C.) or lower satisfying the following expression (1): 270≤TA

公开(公告)号：US20180323118A1

公开(公告)日：2018-11-08

申请号：US16019083

申请日：2018-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Ding Wang ,  An-Jhih Su ,  Chien Ling Hwang ,  Jung Wei Cheng ,  Hsin-Yu Pan ,  Chen-Hua Yu

IPC分类号： H01L23/04 ,  H01L23/00 ,  H01L23/42 ,  H01L21/56 ,  H01L23/10 ,  H01L23/367 ,  H01L23/498

CPC分类号： H01L23/04 ,  H01L21/563 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/023 ,  H01L2224/04026 ,  H01L2224/11616 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/27462 ,  H01L2224/27602 ,  H01L2224/27616 ,  H01L2224/27622 ,  H01L2224/29011 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29147 ,  H01L2224/29166 ,  H01L2224/29181 ,  H01L2224/29187 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29309 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83007 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/163 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/00012 ,  H01L2924/01014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/05442

摘要： An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

公开(公告)号：US20180269176A1

公开(公告)日：2018-09-20

申请号：US15988065

申请日：2018-05-24

申请人： DEXERIALS CORPORATION

发明人： Yasushi AKUTSU

IPC分类号： H01L23/00

CPC分类号： H01L24/32 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29082 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/83203 ,  H01L2224/83851

摘要： An anisotropic electrically conductive film has a structure wherein the electrically conductive particles are disposed on or near the surface of an electrically insulating adhesive base layer, or a structure wherein an electrically insulating adhesive base layer and an electrically insulating adhesive cover layer are laminated together and the electrically conductive particles are disposed near the interface therebetween. Electrically conductive particle groups configured from two or more electrically conductive particles are disposed in a lattice point region of a planar lattice pattern. A preferred lattice point region is a circle centered on a lattice point. A radius of the circle is not less than two times and not more than seven times the average particle diameter of the electrically conductive particles.

公开(公告)号：US20180269128A1

公开(公告)日：2018-09-20

申请号：US15461033

申请日：2017-03-16

申请人： Intel Corporation

发明人： Ameya Limaye ,  Shubhada H. Sahasrabudhe ,  Nachiket R. Raravikar

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/3737 ,  H01L23/42 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/271 ,  H01L2224/27334 ,  H01L2224/29083 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/29355 ,  H01L2224/29357 ,  H01L2224/2936 ,  H01L2224/29471 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/92225 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/01062

摘要： Embodiments of the present disclosure provide techniques and configurations for a computing system with a thermal interface having magnetic particles. In some embodiments, the computing system may include a first part, a second part, and a thermal interface to couple the first and second parts. The thermal interface may comprise a thermal interface material having magnetic particles that are aligned in a defined direction relative to a surface of the first or second part, to provide desired thermal conductivity between the first and second parts. The defined direction of alignment of magnetic particles may comprise an alignment of the particles substantially perpendicularly to the surface of the first or second part. Other embodiments may be described and/or claimed.

公开(公告)号：US10056294B2

公开(公告)日：2018-08-21

申请号：US14325573

申请日：2014-07-08

申请人： Maxim Integrated Products, Inc.

发明人： Vivek S. Sridharan ,  Srikanth Kulkarni ,  Khanh Tran

IPC分类号： H01L21/00 ,  H01L21/78 ,  H01L23/00 ,  H01L23/13 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683 ,  H01L23/498

CPC分类号： H01L21/78 ,  H01L21/4864 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68327 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24137 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83002 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/83912 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/15156 ,  H01L2924/15165 ,  H01L2924/00014 ,  H01L2224/27 ,  H01L2924/014 ,  H01L2224/03

摘要： Semiconductor devices are described that employ techniques configured to control adhesive application between a substrate and a die. In an implementation, a sacrificial layer is provided on a top surface of the die to protect the surface, and bonds pads thereon, from spill-over of the adhesive. The sacrificial layer and spill-over adhesive are subsequently removed from the die and/or chip carrier. In an implementation, the die includes a die attach film (DAF) on a bottom surface of the die for adhering the die to the cavity of the substrate. The die is applied to the cavity with heat and pressure to cause a portion of the die attach film (DAF) to flow from the bottom surface of the die to a sloped surface of the substrate cavity.

公开(公告)号：US10037976B2

公开(公告)日：2018-07-31

申请号：US15704720

申请日：2017-09-14

申请人： INTEL CORPORATION

发明人： Sanka Ganesan ,  Bassam Ziadeh ,  Nitesh Nimkar

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L25/00 ,  H01L25/03 ,  H01L25/10 ,  H01L23/29 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/293 ,  H01L24/02 ,  H01L24/03 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0381 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/27 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/3301 ,  H01L2224/33106 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80903 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

公开(公告)号：US20180197833A1

公开(公告)日：2018-07-12

申请号：US15847083

申请日：2017-12-19

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Akinori SAKAKIBARA

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/492

CPC分类号： H01L24/32 ,  H01L21/4875 ,  H01L23/492 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/26175 ,  H01L2224/29007 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/3201 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/7531 ,  H01L2224/75705 ,  H01L2224/75756 ,  H01L2224/83001 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83385 ,  H01L2224/8384 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The manufacturing method of a semiconductor device includes applying a conductive paste containing metal particles to a specified area in an electrode plate including a recess in a surface of the electrode plate, the specified area being adjacent to the recess. The manufacturing method of a semiconductor device includes placing a semiconductor chip on the conductive paste so that an outer peripheral edge of the semiconductor chip is located above the recess. The manufacturing method of a semiconductor device includes hardening the conductive paste by heating the conductive paste while applying pressure to the semiconductor chip in a direction toward the electrode plate.

公开(公告)号：US20180182728A1

公开(公告)日：2018-06-28

申请号：US15739283

申请日：2016-07-04

申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

发明人： Hisato MICHIKOSHI ,  Hiroshi NOTSU

IPC分类号： H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48

CPC分类号： H01L24/32 ,  H01L21/4882 ,  H01L23/14 ,  H01L23/3675 ,  H01L23/3735 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/3201 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/83203 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： Inexpensive production is achieved while avoiding the degradation of electrical performance caused by the lowering of heat dissipation. The base plate 11 used here has a linear expansion coefficient of 2 to 10 ppm/K, which differs from the linear expansion coefficient of the semiconductor chip 13 by an absolute value of 7 ppm/K or smaller. The bonding layer 12 is formed such that the thickness b thereof is 50 micrometers or smaller, which is thinner than the thickness c of the semiconductor chip 13. Since the thickness b of the bonding layer 12 is thinner than the thickness c of the semiconductor chip 13, the bonding layer 12 upon the heating of the semiconductor chip 13 exhibits thermal expansion that is of relatively small significance, and thus follows the expansion and contraction of the base plate 11. Since the linear expansion coefficient of the base plate 11 is set close to that of the semiconductor chip 13, a displacement occurring between the base plate 11 and the semiconductor chip 13 in response to a temperature change is relatively small.

公开(公告)号：US09997485B2

公开(公告)日：2018-06-12

申请号：US15663802

申请日：2017-07-30

申请人： Semiconductor Components Industries, LLC

发明人： Shutesh Krishnan ,  Yun Sung Won

IPC分类号： H01L23/00 ,  H01L23/495

CPC分类号： H01L24/27 ,  H01L23/49513 ,  H01L23/49524 ,  H01L24/29 ,  H01L24/36 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/27318 ,  H01L2224/27334 ,  H01L2224/29 ,  H01L2224/29006 ,  H01L2224/29101 ,  H01L2224/29199 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83048 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/838 ,  H01L2224/8384 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/37099

摘要： A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

公开(公告)号：US20180151542A1

公开(公告)日：2018-05-31

申请号：US15881238

申请日：2018-01-26

申请人： Micross Advanced Interconnect Technology LLC

发明人： Erik Paul Vick ,  Dorota Temple

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/2511 ,  H01L2224/32145 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01022 ,  H01L2224/83 ,  H01L2224/82

摘要： An electronic package includes an adhesion layer between a first substrate and a second substrate. The adhesion layer is patterned to define openings aligned with through-substrate interconnects and corresponding bond pads. A conductive plane is formed between the first substrate and the second substrate, adjacent to the adhesion layer.