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    Forming contact holes using litho-etch-litho-etch approach
    3.
    发明授权
    Forming contact holes using litho-etch-litho-etch approach 有权

    公开(公告)号：US10916427B2

    公开(公告)日：2021-02-09

    申请号：US16033179

    申请日：2018-07-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

    IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/47

    Abstract: The present invention provides a method for forming a semiconductor device, comprising: first, a target layer is provided, an etching stop layer is formed on the target layer, afterwards, a first photoresist layer is formed on the etching stop layer, and a first etching process is then performed, to forma plurality of first trenches in the etching stop layer. Next, a second photoresist layer is formed on the etching stop layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the etching stop layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the target layer.

    METAL INTERCONNECT STRUCTURE HAVING SERPENT METAL LINE
    8.
    发明申请
    METAL INTERCONNECT STRUCTURE HAVING SERPENT METAL LINE 有权

    公开(公告)号：US20230050928A1

    公开(公告)日：2023-02-16

    申请号：US17472577

    申请日：2021-09-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Che Huang ,  Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

    IPC: H01L23/528 ,  H01L23/522

    Abstract: A semiconductor device includes a first metal interconnection disposed on a substrate, a second metal interconnection disposed on the first metal interconnection, a first contact via disposed between the first metal interconnection and the second metal interconnection, a first serpent metal line connecting to a first end of the first metal interconnection, and a second serpent metal line connecting to a second end of the first metal interconnection. Preferably, the first serpent metal line, the second serpent metal line, and the first metal interconnection are on a same level.

    METHOD FOR FORMING SEMICONDUCTOR DEVICE
    9.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200020576A1

    公开(公告)日：2020-01-16

    申请号：US16033179

    申请日：2018-07-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

    IPC: H01L21/768 ,  H01L21/47 ,  H01L21/02

    Abstract: The present invention provides a method for forming a semiconductor device, comprising: first, a target layer is provided, an etching stop layer is formed on the target layer, afterwards, a first photoresist layer is formed on the etching stop layer, and a first etching process is then performed, to forma plurality of first trenches in the etching stop layer. Next, a second photoresist layer is formed on the etching stop layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the etching stop layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the target layer.

    Method of copper hillock detecting
    10.
    发明授权
    Method of copper hillock detecting 有权

    公开(公告)号：US12007435B2

    公开(公告)日：2024-06-11

    申请号：US17114515

    申请日：2020-12-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Chih Chang ,  Yi-Hsiu Chen ,  Yuan-Fu Ko ,  Chih-Sheng Chang

    IPC: G01R31/28

    CPC classification number: G01R31/2884 ,  G01R31/2894 ,  Y10T29/49004

    Abstract: A method of copper hillock detecting includes the following steps. A testkey structure is disposed on a substrate, wherein the testkey structure includes a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer. A force voltage difference is applied to the lower metallization layer and the upper metallization layer under a test temperature and stress time. A changed sensing voltage difference to the lower metallization layer and the upper metallization layer is detected for detecting copper hillock.

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