公开(公告)号：US10204850B1

公开(公告)日：2019-02-12

申请号：US15624586

申请日：2017-06-15

Applicant: UTAC Headquarters PTE, LTD.

Inventor： Somchai Nondhasitthichai ,  Saravuth Sirinorakul ,  Woraya Benjavasukul

IPC: H01L23/495 ,  H01L23/31

Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top surface, a bottom surface that is opposite the top surface, and side surfaces between the top surface and the bottom surface. Each of the side surfaces includes a step such that the area of the bottom surface is smaller than the area of the top surface. The semiconductor package includes a plurality of contacts that is located at peripheral edges of the bottom surface. Each of the plurality of contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a curved surface located at a corresponding step. In some embodiments, the first surface and the curved surface are plated, while the second surface is exposed (not plated).

公开(公告)号：US09773722B1

公开(公告)日：2017-09-26

申请号：US14706864

申请日：2015-05-07

Applicant: UTAC Headquarters PTE, LTD.

Inventor： Somchai Nondhasitthichai ,  Saravuth Sirinorakul ,  Woraya Benjavasukul

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49582 ,  H01L21/4828 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/014

Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact surfaces. The semiconductor package includes a top surface, a bottom surface that is opposite the top surface, and side surfaces between the top surface and the bottom surface. Each of the side surfaces includes a step such that the area of the bottom surface is smaller than the area of the top surface. The semiconductor package includes a plurality of contacts that is located at peripheral edges of the bottom surface. Each of the plurality of contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a curved surface located at a corresponding step. In some embodiments, the first surface and the curved surface are plated, while the second surface is exposed (not plated).