公开(公告)号：US11641713B2

公开(公告)日：2023-05-02

申请号：US17483824

申请日：2021-09-24

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hung Kuo ,  Kuo-Ching Chen

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09 ,  H05K3/00

Abstract: A circuit board structure, including a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first built-up circuit layer, is provided. The circuit layer includes multiple pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes the pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive via is disposed in the first opening. The first built-up circuit layer is disposed corresponding to the first conductive seed layer region. The first built-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the pads through the first conductive via and the first conductive seed layer region.

公开(公告)号：US12022612B2

公开(公告)日：2024-06-25

申请号：US17662224

申请日：2022-05-05

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hung Kuo

IPC: H05K1/11 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/111 ,  H05K3/4644 ,  H05K1/025

Abstract: The present disclosure provides a circuit board and its manufacturing method. The circuit board includes a first circuit layer, a first conductive post, and a second circuit layer. The first circuit layer includes a first pad and a first seed layer covering a sidewall of the first pad. The first conductive post is on the first pad and directly connected to the first pad. The second circuit layer includes a second pad and a second seed layer covering a sidewall of the second pad. The second pad is on a first connecting end of the first conductive post. The first connecting end is embedded in the second pad, and the second pad is connected to and directly contacts the first connecting end. The first seed layer and the second seed layer do not extend on a sidewall of the first conductive post.

公开(公告)号：US20230314738A1

公开(公告)日：2023-10-05

申请号：US17987770

申请日：2022-11-15

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hung Kuo ,  Tzu-Hsuan Wang

IPC: G02B6/42 ,  G02B6/43 ,  H01L25/16 ,  H04B10/80

CPC classification number: G02B6/4266 ,  G02B6/43 ,  H01L25/167 ,  H04B10/801

Abstract: An electronic device including a light-emitting element, an IC chip, a substrate, an optical waveguide layer, and an optical signal outlet is provided. The IC chip is configured to control the light-emitting element to emit an optical signal. The light-emitting element is disposed on a first surface of the substrate, and the IC chip is disposed on a second surface of the substrate. The optical waveguide layer is disposed on the first surface of the substrate, and the optical waveguide layer includes a core layer, a cladding layer, and a metal layer. The metal layer is disposed on at least a portion of an interface between the core layer and the cladding layer. The optical signal outlet corresponds to the light-emitting element, and the optical signal reaches the optical signal outlet after being transmitted in the core layer.

公开(公告)号：US20220408567A1

公开(公告)日：2022-12-22

申请号：US17683371

申请日：2022-03-01

Applicant: Unimicron Technology Corp.

Inventor： Ke-Chien Li ,  Chun-Hung Kuo ,  Chih-Chun Liang

IPC: H05K3/46 ,  H05K1/11

Abstract: A circuit board includes a substrate, a build-up circuit structure, a graphene oxide layer, a graphene layer, and an insulating material layer. The build-up circuit structure is disposed on the substrate, including at least one inner circuit, at least one dielectric layer, an outer circuit, and multiple conductive vias. The dielectric layer is disposed on the inner circuit. The outer circuit is disposed on the dielectric layer. The conductive vias penetrate the dielectric layer and electrically connect the inner circuit and the outer circuit. The graphene oxide layer and the graphene layer are disposed on the build-up circuit structure at an interval. The graphene oxide layer and the graphene layer are respectively disposed in correspondence to the dielectric layer and the outer circuit. The insulating material layer is disposed on the graphene oxide layer and the graphene layer. The insulating material layer has an opening, which exposes the graphene layer.

公开(公告)号：US11991837B2

公开(公告)日：2024-05-21

申请号：US17683371

申请日：2022-03-01

Applicant: Unimicron Technology Corp.

Inventor： Ke-Chien Li ,  Chun-Hung Kuo ,  Chih-Chun Liang

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K3/4644 ,  H05K1/115

Abstract: A circuit board includes a substrate, a build-up circuit structure, a graphene oxide layer, a graphene layer, and an insulating material layer. The build-up circuit structure is disposed on the substrate, including at least one inner circuit, at least one dielectric layer, an outer circuit, and multiple conductive vias. The dielectric layer is disposed on the inner circuit. The outer circuit is disposed on the dielectric layer. The conductive vias penetrate the dielectric layer and electrically connect the inner circuit and the outer circuit. The graphene oxide layer and the graphene layer are disposed on the build-up circuit structure at an interval. The graphene oxide layer and the graphene layer are respectively disposed in correspondence to the dielectric layer and the outer circuit. The insulating material layer is disposed on the graphene oxide layer and the graphene layer. The insulating material layer has an opening, which exposes the graphene layer.

公开(公告)号：US11792922B2

公开(公告)日：2023-10-17

申请号：US17662432

申请日：2022-05-08

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hung Kuo

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H05K3/32

CPC classification number: H05K1/0271 ,  H05K1/115 ,  H05K1/181 ,  H05K3/32 ,  H05K3/40 ,  H05K2201/068 ,  H05K2201/10378

Abstract: An electronic circuit assembly includes an interposer substrate, a wiring substrate, an electrical connective part and an electronic component. The interposer substrate with a first coefficient of thermal expansion (CTE) includes a first surface, a second surface opposite to the first surface, and a first side surface connecting to the first surface and the second surface. The wiring substrate with a second CTE is disposed below the second surface. The first CTE is lower than the second CTE. The electrical connective part is disposed in the interposer substrate and extends to the first side surface. The electronic component is attached to the first side surface and is electrically connected to the electrical connective part.

公开(公告)号：US12253727B2

公开(公告)日：2025-03-18

申请号：US17987770

申请日：2022-11-15

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hung Kuo ,  Tzu-Hsuan Wang

IPC: G02B6/42 ,  G02B6/43 ,  H01L25/16 ,  H04B10/80

Abstract: An electronic device including a light-emitting element, an IC chip, a substrate, an optical waveguide layer, and an optical signal outlet is provided. The IC chip is configured to control the light-emitting element to emit an optical signal. The light-emitting element is disposed on a first surface of the substrate, and the IC chip is disposed on a second surface of the substrate. The optical waveguide layer is disposed on the first surface of the substrate, and the optical waveguide layer includes a core layer, a cladding layer, and a metal layer. The metal layer is disposed on at least a portion of an interface between the core layer and the cladding layer. The optical signal outlet corresponds to the light-emitting element, and the optical signal reaches the optical signal outlet after being transmitted in the core layer.

公开(公告)号：US20220322529A1

公开(公告)日：2022-10-06

申请号：US17483824

申请日：2021-09-24

Applicant: Unimicron Technology Corp.

Inventor： Chun-Hung Kuo ,  Kuo-Ching Chen

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H05K1/09

Abstract: A circuit board structure, including a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first built-up circuit layer, is provided. The circuit layer includes multiple pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes the pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive via is disposed in the first opening. The first built-up circuit layer is disposed corresponding to the first conductive seed layer region. The first built-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the pads through the first conductive via and the first conductive seed layer region.