公开(公告)号：US10580499B2

公开(公告)日：2020-03-03

申请号：US15710851

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Pang Lu ,  Chi-Hsiu Hsu ,  Chung-Hao Chen ,  Ya-Nan Mou ,  Chung-Cheng Tsai

IPC: G11C16/24 ,  G11C7/18 ,  H01L27/112 ,  H01L27/02 ,  G11C17/12 ,  G06F17/50 ,  G11C7/02

Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.

公开(公告)号：US20250061944A1

公开(公告)日：2025-02-20

申请号：US18370866

申请日：2023-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Hao Chen

IPC: G11C13/00

Abstract: A memory control circuit includes a leakage current providing circuit, a current mirror circuit, an operational circuit and a reference current adjustment circuit. The leakage current providing circuit is used to receive a control signal and provide a leakage current when the control signal has a first enable signal level. The current mirror circuit is used to generate a control current according to the leakage current. The operational circuit is used to generate an enable signal. When the control current is larger than a predetermined value, the enable signal has a second enable signal level. The reference current adjustment circuit is coupled to the operational circuit. When the enable signal has the second enable signal level, the reference current adjustment circuit generates an updated reference current according to a reference current and an adjustment current. The updated reference current is used to determine a resistance of a memory.

公开(公告)号：US20240071535A1

公开(公告)日：2024-02-29

申请号：US17966881

申请日：2022-10-16

Applicant: United Microelectronics Corp.

Inventor： Chung-Hao Chen ,  Chi-Hsiu Hsu ,  Chi-Fa Lien ,  Ying-Ting Lin ,  Cheng-Hsiao Lai ,  Ya-Nan Mou

IPC: G11C17/16 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C17/16 ,  G11C16/0433 ,  G11C16/24

Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

公开(公告)号：US12237027B2

公开(公告)日：2025-02-25

申请号：US17966881

申请日：2022-10-16

Applicant: United Microelectronics Corp.

Inventor： Chung-Hao Chen ,  Chi-Hsiu Hsu ,  Chi-Fa Lien ,  Ying-Ting Lin ,  Cheng-Hsiao Lai ,  Ya-Nan Mou

IPC: G11C17/16 ,  G11C16/04 ,  G11C16/24

Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

公开(公告)号：US11417412B1

公开(公告)日：2022-08-16

申请号：US17189094

申请日：2021-03-01

Applicant: United Microelectronics Corp.

Inventor： Chung-Hao Chen ,  Hsiao-Hua Lu

IPC: G11C29/00 ,  G11C29/50 ,  G11C13/00

Abstract: A cell trace circuit includes a memory cell, a voltage generator and a measuring circuit. The memory cell has a resistor and a memory layer coupled in series to have a top electrode, a middle electrode and a bottom electrode, wherein the resistor and the memory layer are coupled at the middle electrode. The voltage generator provides a test bias to the memory cell ranging from a negative voltage to a positive voltage in a reset path or ranging from the positive voltage to the negative voltage in a set path. The measuring circuit is to determine a current (I) and a voltage (V) crossing the memory layer by the test bias.

公开(公告)号：US20190043587A1

公开(公告)日：2019-02-07

申请号：US15710851

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Pang Lu ,  Chi-Hsiu Hsu ,  Chung-Hao Chen ,  Ya-Nan Mou ,  Chung-Cheng Tsai

IPC: G11C16/24 ,  G11C7/18 ,  G06F17/50 ,  H01L27/02

Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.