公开(公告)号：US10274942B2

公开(公告)日：2019-04-30

申请号：US15476762

申请日：2017-03-31

Applicant: United Microelectronics Corp.

Inventor： Liu-Lian Chen ,  Xian-Feng Du ,  Guo-Hai Zhang

IPC: G05B19/418 ,  G07C3/14

Abstract: A method for determining abnormal equipment in semiconductor manufacturing system includes processing wafers. A measurement data relating to wafers at respective processing steps and at each tool stack run count for respective tools is provided. The method also includes performing statistical and correlation analysis on the production history data and the measurement data to determine multiple parameters including bad ratio (Rb) and good ratio (Rg) for each tool. A first bad-to-good probability ratio (R1) for each tool is obtained by dividing Rb by Rg at the tool stack run count. A second bad-to-good probability ratio (R2) of each tool is an overall probability ratio of Rb to Rg of each tool. A first correlation coefficient (C1) is provided for the measurement data corresponding to the tool stack run count. A second correlation coefficient (C2) is provided for the first bad-to-good probability ratio (R1) corresponding to the tool stack run count.

公开(公告)号：US20180197819A1

公开(公告)日：2018-07-12

申请号：US15400600

申请日：2017-01-06

Applicant: United Microelectronics Corp.

Inventor： Keen Zhang ,  Ji Feng ,  De-Jin Kong ,  Yun-Fei Li ,  Guo-Hai Zhang ,  Ching-Hwa Tey ,  Jing Feng

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53295 ,  H01L23/5283 ,  H01L23/53228

Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.

公开(公告)号：US12094758B2

公开(公告)日：2024-09-17

申请号：US17843089

申请日：2022-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Tsai Hung ,  Yi Liu ,  Guo-Hai Zhang ,  Ching-Hwa Tey

IPC: H01L21/762 ,  H01L23/00 ,  H01L27/12

CPC classification number: H01L21/76251 ,  H01L23/562 ,  H01L23/564 ,  H01L27/1203

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.

公开(公告)号：US10332839B2

公开(公告)日：2019-06-25

申请号：US15400600

申请日：2017-01-06

Applicant: United Microelectronics Corp.

Inventor： Keen Zhang ,  Ji Feng ,  De-Jin Kong ,  Yun-Fei Li ,  Guo-Hai Zhang ,  Ching-Hwa Tey ,  Jing Feng

IPC: H01L21/00 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.

公开(公告)号：US20180239340A1

公开(公告)日：2018-08-23

申请号：US15476762

申请日：2017-03-31

Applicant: United Microelectronics Corp.

Inventor： Liu-Lian Chen ,  Xian-Feng Du ,  Guo-Hai Zhang

IPC: G05B19/418 ,  G06F17/18

CPC classification number: G05B19/4184 ,  G05B2219/32191 ,  G05B2219/45032 ,  G07C3/14 ,  Y02P90/02 ,  Y02P90/14

Abstract: A method for determining abnormal equipment in semiconductor manufacturing system includes processing wafers. A measurement data relating to wafers at respective processing steps and at each tool stack run count for respective tools is provided. The method also includes performing statistical and correlation analysis on the production history data and the measurement data to determine multiple parameters including bad ratio (Rb) and good ratio (Rg) for each tool. A first bad-to-good probability ratio (R1) for each tool is obtained by dividing Rb by Rg at the tool stack run count. A second bad-to-good probability ratio (R2) of each tool is an overall probability ratio of Rb to Rg of each tool. A first correlation coefficient (C1) is provided for the measurement data corresponding to the tool stack run count. A second correlation coefficient (C2) is provided for the first bad-to-good probability ratio (R1) corresponding to the tool stack run count.