公开(公告)号：US20210020247A1

公开(公告)日：2021-01-21

申请号：US17030124

申请日：2020-09-23

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhaobing Li ,  Chi Ren

IPC: G11C16/04 ,  H01L45/00 ,  G11C13/00 ,  H01L27/11517

Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

公开(公告)号：US11100995B2

公开(公告)日：2021-08-24

申请号：US17030124

申请日：2020-09-23

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhaobing Li ,  Chi Ren

IPC: G11C16/04 ,  H01L45/00 ,  G11C13/00 ,  H01L27/11517

Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

公开(公告)号：US09553188B1

公开(公告)日：2017-01-24

申请号：US14970549

申请日：2015-12-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lingzi Li ,  Zhaobing Li ,  Hui Lu ,  Zhang Hu Sun

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/7835 ,  H01L29/0607 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7816

Abstract: A high-voltage semiconductor device includes a semiconductor substrate, a gate structure, a drain, an insulation structure, and a plurality of conductive structures. The insulation structure is disposed in the semiconductor substrate and disposed between the gate structure and the drain. The insulation structure includes a plurality of insulation units disposed separately from one another. Each of the conductive structures is embedded in one of the insulation units.

Abstract translation: 高压半导体器件包括半导体衬底，栅极结构，漏极，绝缘结构和多个导电结构。 绝缘结构设置在半导体衬底中并且设置在栅极结构和漏极之间。 绝缘结构包括彼此分开设置的多个绝缘单元。 每个导电结构都嵌入绝缘单元之一中。

公开(公告)号：US10825522B2

公开(公告)日：2020-11-03

申请号：US16173406

申请日：2018-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhaobing Li ,  Chi Ren

IPC: G11C16/04 ,  H01L45/00 ,  G11C13/00 ,  H01L27/11517

Abstract: A structure of nonvolatile memory device includes a substrate, having a logic device region and a memory cell region. A first gate structure for a low-voltage transistor is disposed over the substrate in the logic device region, wherein the first gate structure comprises a single-layer polysilicon. A second gate structure for a memory cell is disposed over the substrate in the memory cell region. The second gate structure includes a gate insulating layer on the substrate. A floating gate layer is disposed on the gate insulating layer, wherein the floating gate layer comprises a first polysilicon layer and a second polysilicon layer as a stacked structure. A memory dielectric layer is disposed on the floating gate layer. A control gate layer is disposed on the memory dielectric layer, wherein the control gate layer and the single-layer polysilicon are originated from a preliminary polysilicon layer in same.

公开(公告)号：US08921913B1

公开(公告)日：2014-12-30

申请号：US13923374

申请日：2013-06-21

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yuan Hsu ,  Zhaobing Li ,  Chi Ren ,  Ching-Long Tsai ,  Wei Cheng

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L21/3212

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract translation: 浮栅形成工艺包括以下步骤。 提供了包含通过从衬底突出的隔离结构彼此隔离的有源区的衬底。 第一导电材料形成为保形地覆盖有源区域和隔离结构。 对第一导电材料进行回蚀处理，以分别形成在有源区域中彼此分离的浮动栅极。