公开(公告)号：US20230299160A1

公开(公告)日：2023-09-21

申请号：US18199967

申请日：2023-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  Xiaojuan Gao ,  CHI REN

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/66825 ,  H01L29/40114 ,  H01L29/7883

Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.

公开(公告)号：US20220352195A1

公开(公告)日：2022-11-03

申请号：US17864435

申请日：2022-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  CHI REN

IPC: H01L27/11578 ,  H01L29/66 ,  H01L27/11551 ,  H01L29/78

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US20180366478A1

公开(公告)日：2018-12-20

申请号：US15626179

申请日：2017-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chih-Chien Chang ,  Shen-De Wang

IPC: H01L27/11521 ,  H01L27/11556

CPC classification number: H01L27/11521 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788

Abstract: A nonvolatile memory cell includes a substrate having a drain region, a source region, and a channel region between the drain region and the source region. A floating gate and a select gate are disposed on the channel region. A control gate is disposed on the floating gate. An erase gate is disposed on the source region. The erase gate includes a lower end portion that extends into a major surface of the substrate.

公开(公告)号：US09852912B1

公开(公告)日：2017-12-26

申请号：US15270638

申请日：2016-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Liang Yi ,  Wen-Bo Ding ,  Chien-Kee Pang ,  Yu-Yang Chen

IPC: H01L21/4763 ,  H01L21/28 ,  H01L27/11521

CPC classification number: H01L21/28273

Abstract: A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.

公开(公告)号：US11882699B2

公开(公告)日：2024-01-23

申请号：US17224100

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren

IPC: H10B43/20 ,  H01L29/78 ,  H01L29/66 ,  H10B41/20

CPC classification number: H10B43/20 ,  H01L29/66795 ,  H01L29/7851 ,  H10B41/20

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US11699730B2

公开(公告)日：2023-07-11

申请号：US17510371

申请日：2021-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Xiaojuan Gao ,  Chi Ren

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

Abstract: A semiconductor memory device includes a substrate; a source diffusion region in the substrate; a pair of floating gates disposed on opposite of the source diffusion region; a first dielectric cap layer disposed directly on each of the floating gates; an erase gate disposed on the source diffusion region and partially overlapping an upper inner corner of each of the floating gates; a second dielectric cap layer disposed on the erase gate and the first dielectric cap layer; a select gate disposed on a sidewall of the first dielectric cap layer; and a drain diffusion region disposed in the substrate and adjacent to the select gate.

公开(公告)号：US20200373436A1

公开(公告)日：2020-11-26

申请号：US16452311

申请日：2019-06-25

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren

IPC: H01L29/792 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66

Abstract: A structure of a memory device and a fabrication method thereof are provided. The structure of the memory device includes a tunneling layer disposed on a substrate. A first oxide/nitride/oxide (ONO) layer is disposed on the substrate abutting to the tunneling layer. A floating gate is disposed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer. A second ONO layer is disposed on the floating gate. A control gate is disposed on the second ONO layer. An isolation layer is disposed on first sidewalls of the floating gate and sidewalls of the control gate. An erase gate is disposed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.

公开(公告)号：US10192874B2

公开(公告)日：2019-01-29

申请号：US15626179

申请日：2017-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chih-Chien Chang ,  Shen-De Wang

IPC: H01L29/788 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/66 ,  H01L29/423

Abstract: A nonvolatile memory cell includes a substrate having a drain region, a source region, and a channel region between the drain region and the source region. A floating gate and a select gate are disposed on the channel region. A control gate is disposed on the floating gate. An erase gate is disposed on the source region. The erase gate includes a lower end portion that extends into a major surface of the substrate.

公开(公告)号：US20170221911A1

公开(公告)日：2017-08-03

申请号：US15081946

申请日：2016-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/115 ,  G11C16/14 ,  H01L21/28 ,  G11C16/10 ,  H01L21/3205 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  G11C16/04 ,  H01L21/311

CPC classification number: H01L29/40114 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32055 ,  H01L27/11524 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: The flash memory includes a stacked gate disposed on a substrate. The stacked gate includes an erase gate and two floating gates. Each floating gate has an acute angle pointing toward the erase gate. There is a high electric field formed around the acute angle so that the flash memory can perform an erase mode even at a lower operational voltage. Furthermore, the flash memory does not use any control gate to perform a write mode.

公开(公告)号：US20240332384A1

公开(公告)日：2024-10-03

申请号：US18739341

申请日：2024-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  CHI REN

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

Abstract: A semiconductor memory device includes a substrate, an active region defined in the substrate by a trench isolation structure, a pair of floating gates on the substrate and at two sides of a fish-bone shaped recessed region of the active region, a source line doped region in the fish-bone shaped recessed region of the active region, wherein a bottom surface of the source line doped region extends above a bottom surface of the trench isolation structure, an erase gate disposed between the floating gates and on the source line doped region, a word line disposed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate, and a bit line doped region in the substrate and adjacent to the word line.