公开(公告)号：US20210305051A1

公开(公告)日：2021-09-30

申请号：US17004031

申请日：2020-08-27

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Shida DONG ,  Zhengkang WANG ,  Dong FANG ,  Zhuo WANG ,  Bo ZHANG

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L21/765 ,  H01L29/66

Abstract: A metal wiring method for reducing gate resistance of a narrow control gate structure, wherein the gate structure is etched with first gate electrodes and second gate electrodes at regular intervals and kept with complete gate electrodes at regular intervals, thereby constituting a structure in which the first and second gate electrodes and the complete gate electrodes are spaced apart. A first contact hole is etched on the complete gate electrode to draw out metal as a first metal layer. A second contact hole is etched on a source region and a split gate to draw out metal as a second metal layer. These two metal layers are separated by a dielectric layer. A multi-point contact of the first layer of metal with the gate electrode in a Y direction reduces the gate resistance caused by an excessively long path in the Y direction of a control gate electrode.

公开(公告)号：US20210336052A1

公开(公告)日：2021-10-28

申请号：US17005354

申请日：2020-08-28

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Zhengkang WANG ,  Shida DONG ,  Bo ZHANG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423

Abstract: A power MOS device with low gate charge and a method for manufacturing the same. The device includes an M-shaped gate structure, which reduces the overlapped area between control gate electrode and split gate electrode. A low-k material is introduced to reduce dielectric constant of the isolation medium material. The combination of the M-shaped gate structure and low-k material can reduce parasitic capacitance Cgs of the device, thereby increasing switching speed and reducing switching losses.