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1.发明授权公开(公告)号：US11126544B2
公开(公告)日：2021-09-21
申请号：US15378041
申请日：2016-12-14
Applicant: VIA Technologies, Inc.
Inventor： Ying Yu Tai , Jiangli Zhu
Abstract: A non-volatile memory (NVM) apparatus and a garbage collection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller is coupled to the NVM. The controller accesses the NVM according to a logical address of a write command of a host. The controller performs the garbage collection method to release space occupied by invalid data. The garbage collection method includes: grouping a plurality of blocks of the NVM into a plurality of tiers according to hotness of data, moving valid data in one closed source block of a hotter tier among the tiers to one open target block of a cooler tier among the tiers, and erasing the closed source block of the hotter tier to release space.
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公开(公告)号：US10141953B2
公开(公告)日：2018-11-27
申请号：US15379450
申请日：2016-12-14
Applicant: VIA Technologies, Inc.
Inventor： Ying Yu Tai , Jiangli Zhu
Abstract: A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.
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公开(公告)号：US10050643B2
公开(公告)日：2018-08-14
申请号：US15379454
申请日：2016-12-14
Applicant: VIA Technologies, Inc.
Inventor： Ying Yu Tai , Jiangli Zhu
CPC classification number: H03M13/1128 , G06F11/1012
Abstract: The LDPC apparatus includes an LDPC iteration calculating circuit, a decision-bit storage circuit, and a convergence detection circuit. The LDPC iteration calculating circuit performs an LDPC iteration calculation to obtain a new decision bit value of a corresponding variable node. The decision-bit storage circuit uses the new decision bit value to update one corresponding old decision bit value among a plurality of old decision bit values. The convergence detection circuit stores check sums of a plurality of check nodes. The convergence detection circuit uses the new decision bit value and the corresponding old decision bit value to update one corresponding check sum among the check sums. The convergence detection circuit determines whether the LDPC iteration calculation is converged based on the check sums of the check nodes.
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公开(公告)号：US20180167087A1
公开(公告)日：2018-06-14
申请号：US15379454
申请日：2016-12-14
Applicant: VIA Technologies, Inc.
Inventor： Ying Yu Tai , Jiangli Zhu
CPC classification number: H03M13/255 , G06F11/1004 , G06F11/1096 , H03M13/3746
Abstract: The LDPC apparatus includes an LDPC iteration calculating circuit, a decision-bit storage circuit, and a convergence detection circuit. The LDPC iteration calculating circuit performs an LDPC iteration calculation to obtain a new decision bit value of a corresponding variable node. The decision-bit storage circuit uses the new decision bit value to update one corresponding old decision bit value among a plurality of old decision bit values. The convergence detection circuit stores check sums of a plurality of check nodes. The convergence detection circuit uses the new decision bit value and the corresponding old decision bit value to update one corresponding check sum among the check sums. The convergence detection circuit determines whether the LDPC iteration calculation is converged based on the check sums of the check nodes.
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5.发明授权公开(公告)号：US09747974B2
公开(公告)日：2017-08-29
申请号：US15172162
申请日：2016-06-03
Applicant: VIA Technologies, Inc.
Inventor： Ying Yu Tai , Jiangli Zhu
CPC classification number: G11C11/5642 , G06F11/1072 , G11C16/26 , G11C16/3427 , G11C29/52 , G11C2029/0409
Abstract: A non-volatile memory apparatus includes a non-volatile storage circuit and a controller. The non-volatile storage circuit reads a corresponding data voltage set, and converts the corresponding data voltage set to the corresponding data in accordance with the read-voltage parameter of the controller. The controller decides whether to perform the on-the-fly self-adaptive read-voltage adjustment in accordance with the number of error bits of the corresponding data. The on-the-fly self-adaptive read-voltage adjustment includes: providing a left (or lower) read-voltage parameter to the non-volatile storage circuit for converting the corresponding data voltage set to the left corresponding data; providing a right (or higher) read-voltage parameter to the non-volatile storage circuit for converting the corresponding data voltage set to the right corresponding data; and deciding the adjusting-direction and the adjusting-amount of the read-voltage parameter in accordance with the relationship between the corresponding data, the left corresponding data and the right corresponding data.
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Patent Agency Ranking
公开(公告)号：US20180165010A1
公开(公告)日：2018-06-14
申请号：US15378044
申请日：2016-12-14
Applicant: VIA Technologies, Inc.
Inventor： Ying Yu Tai , Jiangli Zhu
Abstract: A non-volatile memory (NVM) apparatus and an iteration sorting method thereof are provided. The NVM apparatus performs the iteration sorting method to select one target block from a plurality of blocks of a NVM, and to perform a management operation on the target block. The iteration sorting method includes: selecting a plurality of candidate blocks among the blocks of the NVM to join into a sorting set, sorting all of the candidate blocks in the sorting set according to metadata, picking one candidate block with maximum (or minimum) metadata from the sorting set to serve as the target block, and keeping M candidate blocks in the sorting set and discarding the rest of the candidate blocks from the sorting set.
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公开(公告)号：US10824554B2
公开(公告)日：2020-11-03
申请号：US15378044
申请日：2016-12-14
Applicant: VIA Technologies, Inc.
Inventor： Ying Yu Tai , Jiangli Zhu
Abstract: A non-volatile memory (NVM) apparatus and an iteration sorting method thereof are provided. The NVM apparatus performs the iteration sorting method to select one target block from a plurality of blocks of a NVM, and to perform a management operation on the target block. The iteration sorting method includes: selecting a plurality of candidate blocks among the blocks of the NVM to join into a sorting set, sorting all of the candidate blocks in the sorting set according to metadata, picking one candidate block with maximum (or minimum) metadata from the sorting set to serve as the target block, and keeping M candidate blocks in the sorting set and discarding the rest of the candidate blocks from the sorting set.
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公开(公告)号：US10303536B2
公开(公告)日：2019-05-28
申请号：US15265909
申请日：2016-09-15
Applicant: VIA TECHNOLOGIES, INC.
Inventor： Ying Yu Tai , Jiangli Zhu
Abstract: A non-volatile memory device including a non-volatile memory and a controller is provided. The non-volatile memory includes a plurality of closed blocks and a plurality of open blocks. The controller derives a ratio value according to the write workload of the non-volatile memory between a first time point and a second time point and then performs a patrol read on a portion of the closed blocks according to the ratio value.
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公开(公告)号：US10049007B2
公开(公告)日：2018-08-14
申请号：US15243323
申请日：2016-08-22
Applicant: VIA TECHNOLOGIES, INC.
Inventor： Jiangli Zhu , Ying Yu Tai
Abstract: A non-volatile memory device including a non-volatile memory and a controller is provided. The controller establishes a standard table and at least one priority table according to a read table stored in the non-volatile memory. The probability that the controller utilizes the read voltages corresponding to the indexes recorded in the priority table to read and successfully decode the codewords stored in non-volatile memory is high. When the controller utilizes the read voltages corresponding to the indexes recorded in the priority table to read and unsuccessfully decode the codewords, the controller utilizes the read voltages corresponding to the indexes recorded in the standard table to read and decode the codewords stored in non-volatile memory.
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公开(公告)号：US20170277589A1
公开(公告)日：2017-09-28
申请号：US15221598
申请日：2016-07-28
Applicant: VIA Technologies, Inc.
Inventor： Ying Yu Tai , Jiangli Zhu
CPC classification number: G06F11/1068 , G11C29/52 , H03M13/1105 , H03M13/1128
Abstract: A non-volatile memory (NVM) apparatus and an empty page detection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller reads the content of a memory page of the NVM. The controller performs Low Density Parity Check (LDPC) decoding for at least one codeword of the memory page to obtain a decoded codeword and a check-result vector. The controller determines that the memory page is not an empty page when the LDPC decoding for the codeword is successful. The controller counts an amount of the bits being 1 (or 0) in the check-result vector when the LDPC decoding for the codeword is fail. Based on the amount of the bits being 1 (or 0) in the check-result vector, the controller determines whether the memory page is an empty page.
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