公开(公告)号：US10733107B2

公开(公告)日：2020-08-04

申请号：US15287743

申请日：2016-10-07

Applicant: VIA Technologies, Inc.

Inventor： Ying-Yu Tai ,  Jiangli Zhu ,  Jiin Lai

IPC: G06F12/10 ,  G06F12/1009 ,  G06F3/06 ,  G06F12/02

Abstract: A non-volatile memory (NVM) apparatus and an address classification method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller accesses the NVM in accordance with a write command of a host. The controller may perform the address classification method. The address classification method includes: providing a data look-up table, wherein the data look-up table includes a plurality of data entries, each of the data entries includes a logical address information, a counter value and a timer value; searching the data look-up table based on the logical address of the write command in order to obtain a corresponding counter value and a corresponding timer value; and determining whether the logical address of the write command is a hot data address based on the corresponding counter value and the corresponding timer value.

公开(公告)号：US20180165010A1

公开(公告)日：2018-06-14

申请号：US15378044

申请日：2016-12-14

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: G06F3/06 ,  G11C16/34 ,  G06F12/02

Abstract: A non-volatile memory (NVM) apparatus and an iteration sorting method thereof are provided. The NVM apparatus performs the iteration sorting method to select one target block from a plurality of blocks of a NVM, and to perform a management operation on the target block. The iteration sorting method includes: selecting a plurality of candidate blocks among the blocks of the NVM to join into a sorting set, sorting all of the candidate blocks in the sorting set according to metadata, picking one candidate block with maximum (or minimum) metadata from the sorting set to serve as the target block, and keeping M candidate blocks in the sorting set and discarding the rest of the candidate blocks from the sorting set.

公开(公告)号：US10372533B2

公开(公告)日：2019-08-06

申请号：US15221598

申请日：2016-07-28

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: G06F11/10 ,  H03M13/11 ,  G11C29/52

Abstract: A non-volatile memory (NVM) apparatus and an empty page detection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller reads the content of a memory page of the NVM. The controller performs Low Density Parity Check (LDPC) decoding for at least one codeword of the memory page to obtain a decoded codeword and a check-result vector. The controller determines that the memory page is not an empty page when the LDPC decoding for the codeword is successful. The controller counts an amount of the bits being 1 (or 0) in the check-result vector when the LDPC decoding for the codeword is fail. Based on the amount of the bits being 1 (or 0) in the check-result vector, the controller determines whether the memory page is an empty page.

公开(公告)号：US10318202B2

公开(公告)日：2019-06-11

申请号：US15641242

申请日：2017-07-04

Applicant: VIA Technologies, Inc.

Inventor： Tingjun Xie ,  Ying Yu Tai ,  Jiangli Zhu

IPC: G06F3/06 ,  G06F11/10 ,  H03M13/11 ,  H03M13/00 ,  H03M7/30

Abstract: A non-volatile memory (NVM) apparatus and a data de-duplication method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller performs an error checking and correcting (ECC) method to convert a raw data into an encoded data. The controller performs the data de-duplication method to reduce a number of times that the same encoded data is repeatedly written into the NVM. The controller generates the feature information corresponding to the raw data by reusing the ECC method. When the feature information is found in a feature list, the encoded data corresponding to the raw data will not be written into the NVM. When the feature information is not found in the feature list, the feature information is added into the feature list, and the encoded data corresponding to the raw data is written into the NVM.

公开(公告)号：US10055288B2

公开(公告)日：2018-08-21

申请号：US15225846

申请日：2016-08-02

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiin Lai ,  Jiangli Zhu

IPC: H03M13/00 ,  G06F11/10 ,  G06F3/06 ,  G11C16/04 ,  G11C29/04

CPC classification number: G06F11/1072 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/1068 ,  G11C16/0483 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ECC) circuit and a controller. The controller is coupled to the non-volatile memory and the ECC circuit. The controller may access a target wordline of the non-volatile memory in accordance with a physical address. The controller groups a plurality of wordlines of the non-volatile memory into a plurality of wordline groups, wherein different wordline groups have different codeword structures. The controller controls the ECC circuit according to the codeword structure of the wordline group of the target wordline, and the ECC circuit generates a codeword to be stored in the target wordline or check a codeword from the target wordline under control of the controller.

公开(公告)号：US20170212801A1

公开(公告)日：2017-07-27

申请号：US15225846

申请日：2016-08-02

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiin Lai ,  Jiangli Zhu

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C16/04

CPC classification number: G06F11/1072 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/1068 ,  G11C16/0483 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ECC) circuit and a controller. The controller is coupled to the non-volatile memory and the ECC circuit. The controller may access a target wordline of the non-volatile memory in accordance with a physical address. The controller groups a plurality of wordlines of the non-volatile memory into a plurality of wordline groups, wherein different wordline groups have different codeword structures. The controller controls the ECC circuit according to the codeword structure of the wordline group of the target wordline, and the ECC circuit generates a codeword to be stored in the target wordline or check a codeword from the target wordline under control of the controller.

公开(公告)号：US20180267733A1

公开(公告)日：2018-09-20

申请号：US15641242

申请日：2017-07-04

Applicant: VIA Technologies, Inc.

Inventor： Tingjun Xie ,  Ying Yu Tai ,  Jiangli Zhu

IPC: G06F3/06 ,  G06F11/10 ,  H03M13/11

CPC classification number: G06F3/0641 ,  G06F3/0608 ,  G06F3/0656 ,  G06F3/0679 ,  G06F11/1048 ,  G06F11/1076 ,  H03M13/1128 ,  H03M13/1148

Abstract: A non-volatile memory (NVM) apparatus and a data de-duplication method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller performs an error checking and correcting (ECC) method to convert a raw data into an encoded data. The controller performs the data de-duplication method to reduce a number of times that the same encoded data is repeatedly written into the NVM. The controller generates the feature information corresponding to the raw data by reusing the ECC method. When the feature information is found in a feature list, the encoded data corresponding to the raw data will not be written into the NVM. When the feature information is not found in the feature list, the feature information is added into the feature list, and the encoded data corresponding to the raw data is written into the NVM.

公开(公告)号：US20180167086A1

公开(公告)日：2018-06-14

申请号：US15379450

申请日：2016-12-14

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: H03M13/25 ,  H03M13/37 ,  H03M13/00

CPC classification number: H03M13/3753 ,  G11C29/00 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  H03M13/1111 ,  H03M13/1117 ,  H03M13/1142 ,  H03M13/175 ,  H03M13/658

Abstract: A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.

公开(公告)号：US20180165189A1

公开(公告)日：2018-06-14

申请号：US15378041

申请日：2016-12-14

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0679 ,  G06F2212/7205

Abstract: A non-volatile memory (NVM) apparatus and a garbage collection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller is coupled to the NVM. The controller accesses the NVM according to a logical address of a write command of a host. The controller performs the garbage collection method to release space occupied by invalid data. The garbage collection method includes: grouping a plurality of blocks of the NVM into a plurality of tiers according to hotness of data, moving valid data in one closed source block of a hotter tier among the tiers to one open target block of a cooler tier among the tiers, and erasing the closed source block of the hotter tier to release space.

公开(公告)号：US20170206953A1

公开(公告)日：2017-07-20

申请号：US15172162

申请日：2016-06-03

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: G11C11/56 ,  G11C16/34 ,  G11C29/52 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G06F11/1072 ,  G11C16/26 ,  G11C16/3427 ,  G11C29/52 ,  G11C2029/0409

Abstract: A non-volatile memory apparatus includes a non-volatile storage circuit and a controller. The non-volatile storage circuit reads a corresponding data voltage set, and converts the corresponding data voltage set to the corresponding data in accordance with the read-voltage parameter of the controller. The controller decides whether to perform the on-the-fly self-adaptive read-voltage adjustment in accordance with the number of error bits of the corresponding data. The on-the-fly self-adaptive read-voltage adjustment includes: providing a left (or lower) read-voltage parameter to the non-volatile storage circuit for converting the corresponding data voltage set to the left corresponding data; providing a right (or higher) read-voltage parameter to the non-volatile storage circuit for converting the corresponding data voltage set to the right corresponding data; and deciding the adjusting-direction and the adjusting-amount of the read-voltage parameter in accordance with the relationship between the corresponding data, the left corresponding data and the right corresponding data.